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Layout-based ESD Checking Methodology at Nvidia

Layout-based ESD Checking Methodology at Nvidia
by Daniel Payne on 10-14-2013 at 12:43 pm

The company Nvidiais synonymous with designing all things video and GPU, so I watched Ting Ku, director of engineering at an archived webinar today talk about: Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Macro-level Dynamic Solutions.

ESD Emerging Issues

As the technology nodes transition to smaller geometries the susceptibility to ESD failures are increasing because of thinner oxides used in MOS devices, lower junction thermal breakdown voltages, and lower current density limits.

Static Flow

One of the first ESD checks that Nvidia runs on their IC layout is to measure static resistance and current densities. The purpose is to find and fix layout violations in the resistance and current density values.

A commercial EDA tool from Apachecalled PathFinder is used to automate these particular checks. All of the different paths need to be identified thoroughly without relying on manual methods. A specific run of PathFinder took 5.5 hours for a full-chip static resistance analysis while checking some 16,066 clamp-diode pairs and 826 bump to clamp resistance paths.

Violations of the Shortest Resistance Path Tracing (SPT) are shown below in Yellow on the right in a list, then with red arrows on the IC layout on the left:

In addition to resistance checks you also need current density checks for ESD events. Any violations of current density are shown highlighted in the IC layout as well:

Dynamic Flow

Some ESD failures can only be analyzed with dynamic checking, however you must be an ESD expert in order to get meaningful results. The basic idea is to identify the worst transient voltage-stressed junctions, then make sure that you have clamps placed properly.

An example of why you need dynamic analysis is shown below in a cross-domain check when you want to see the discharge between VDD1 through the MOS device highlighted to GND. The discharge time for the path shown in Red will be different than the path shown in Blue, which will create a gradient voltage of Vgs across the MOS device. Only a dynamic check can calculate that Vgs value as a function of time.

For accuracy in dynamic simulation you need to model effects like:

  • Snap-back voltage in clamp
  • Power and Ground RLC and coupled signal RC
  • Substrate RC and well-diodes
  • Nonlinear device modeling with high voltage

In addition, the simulator needs to handle the large capacity of post-layout netlists (blocks, not full chip yet), and run fast enough to get results in hours. An example dynamic simulation with 62,256 MOS devices, 541 diodes and 2,709,648 RLCs ran in 3 hours 25 minutes, requiring 25 GB of peak RAM, and a setup time of 1 hour 20 minutes.

One downside of dynamic simulation is that you must decide which areas to test, and in one case an untested area did fail in silicon causing a re-spin. Engineers at Nvidia where able to then dynamically simulate the failing area and identify two areas of the layout that required changes to conform.

Future ESD Issues

How do you design a 3D-IC to be ESD tolerant? Nvidia recommends ESD levels of 500V for HBM (Human Body Model) and 250V for CDM (Charged Device Model).

Can you add diodes to a FinFET device for ESD compliance?

Nvidia is using both static and dynamic ESD analysis methods in the design of their GPU devices. Silicon tests for ESD compliance correlated well with simulated results provided by Apache tools. If you simulate both static and dynamic ESD checks prior to tape-out, then your chance for first silicon success goes up. If you do have ESD failures in the field, then you can pinpoint and fix them using this tool-based methodology.

lang: en_US

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