WP_Term Object
    [term_id] => 109
    [name] => Imagination Technologies
    [slug] => imagination-technologies
    [term_group] => 0
    [term_taxonomy_id] => 109
    [taxonomy] => category
    [description] => 
    [parent] => 14433
    [count] => 37
    [filter] => raw
    [cat_ID] => 109
    [category_count] => 37
    [category_description] => 
    [cat_name] => Imagination Technologies
    [category_nicename] => imagination-technologies
    [category_parent] => 14433

Enter the Warrior

Enter the Warrior
by Paul McLellan on 10-14-2013 at 11:57 am

 Since Imagination’s acquisition of MIPS at the end of last year, the MIPS product line has been given a new lease of life. There are two things driving this. The first is simply that with its new home, the MIPS architecture has a solid future whereas before it was uncertain. Secondly, Imagination moved their own general purpose processor designers onto the MIPS team so that there is a lot more manpower working on the cores.

Back in June Imagination/MIPS previewed some information about the architectural direction. Back then I wrote about it here. The new core, the MIPS Series5 Warrior P5600, was officially announced today. It has:

  • 1.2X-2X gains on system-oriented software workloads
  • similar power envelope
  • 1-2+ GHz implementation range in TSMC 28HPM
  • proven MIPS architecture used for 30 years
  • full binary compatibility: low end 32 bit to high end 64 bit
  • best in class branch prediction
  • hardware virtualization: each guest has TLB and COP0 context so no operating system modifications are necessary to run as a guest
  • architectural support for hardware multi-threading
  • coherent multi-core configurations up to 6 cores
  • advanced SIMD
  • superior security
  • common tool chain
  • extensive 32 bit and 64 bit ecosystems
  • eXtended Physical Addressing (40 bits) provides for use of physical memory up to a terabyte
  • enhanced virtual addressing for kernel/user mapping

The P5600 is optimized for peak single thread performance. It is a superscalar multi-issue out-of-order design with a 16 stage pipeline. At peak it can have 4X fetch, 3X dispatch, 4X integer and 2X SIMD issue. The datapath has been widened giving lower latencies. Some additional tricks result in maximum utilization of the pipeline especially doing copies with load/store instruction bonding which bonds 2 32-bit integer or two 64-bit floating point accesses per cycle.

With 6 P5600 cores the Warrior delivers 35,000 DMIPS, 50,000 CoreMark (at 1.7GHz). But this is just the first of a wave of Series5 Warrior generation CPUs. It is available for licensing and silicon design this quarter.

More information about the P5600 is here including a lot more detail than I can get into this blog post.

Also, the Imagination Developers Conference IDC13 in San Francisco is tomorrow. Details and registration are here.

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