Apache Presents: ESD analysis

The 26th Conference on VLSI Design will be in Pune, India from January 5th to 10th at the Hyatt Regency. Details on the conference here. Registration here. I happened to be involved in the first of these conferences, which was held in Edinburgh where I was wrapping up my PhD. It was in the considerably less palatial surroundings of the Appleton Tower before it was modernized and was run on a shoe-string. We would have been surprised to have a time-traveler come back and tell us that the conference would still be going in 2013 and perhaps even more surprised that it would be in India.

At next month’s conference, Apache (I guess you all know it is a subsidiary of Ansys by now, don’t you) is presenting a paper jointly with nVidia

The paper is on Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Maco-level Dynamic Solutions, presented by Norman Chang and Jai Pollayil of Apache and Ting-Sheng Ku of nVidia on 9th January from 11am to 12.20pm (the dreaded presentation spot being between the audience and lunch). By the way, I love the way the sessions are called “pre-lunch”, “post-lunch” and “post-afternoon-tea”. Bit like a cricket test match (which, for Americans and others who are totally bemused by cricket, takes place over 5 days with meal breaks, makes baseball seem like a blink of an eye).

The paper examines the comprehensive ESD static/dynamic methodology that was developed for failure diagnosis and predictive simulation of improvements. This methodology focused on full-chip static and dynamic analysis including modeling of die-level metal grid, substrate grid and well diode, package effective capacitance, and pogo pin. The paper includes real-world human body model (HBM) and charged device model (CDM) applications.

The paper focuses on an integrated methodology for how a full-chip static and block-based dynamic ESD methodology provides comprehensive coverage on HBM/CDM issues, which are resistive-dominant, and the dynamic problems that require more detailed RLC and transistor-level modeling. This methodology uses PathFinder, an Apache tool that performs full-chip static analysis and constructs dynamic ESD circuits with complete parasitic models in simulation.