I switched to Aldec Active-HDL

I have written this before, but I was a ModelSim snob. That has changed after trying Active-HDL from Aldec. I have no plans on going back to ModelSim. You ask why? Well astute reader, great question. Unfortunately these blogs are text limited and there is no way to write about all the bells and whistles of Active-HDL. So before I continue, please go to this Active-HDL download link and evaluate for yourself, I assure you will not be sorry. I know this is word salad, but they also have great customer service (real people). After installing you will be up in running in minutes without even reading the instructions, go men!

Where do I begin…? Active-HDL, is a design environment. In this environment you have a compiler, simulator, IP generator, debugger, text editor (which by the way highlights where your compile errors are, I love that feature, not that I have errors), test bench generator, waveform compare, Code to graphics, version control, (very cool) and the list goes on and on. Seriously, if I listed all the features, I would run out of blog. Active-HDL is friendly to all FPGAs and you can link the tool to your FPGA environments.

Whether we like it or not, RTL simulation is a fact of FPGA life, so why not use a flexible environment? When I use the GUI, I feel like the designers know what I’m thinking. So here is how I began, you can start with a reference design, or use one you already have. I started with a design I already had. Simply follow the prompts, name your project and add your Verilog or VHDL. About 20 seconds later I’m compiling. The design I had, did NOT have a testbed, I was using hardware in the loop. I went to the ‘tools tab’ and clicked generate test bench! It worked! Then I opened the testbed file and added my clock, resets etc.. And I’m off and running. To be honest with you, I was a bit overwhelmed with all the swizzles the tool has. You even can custom tweak the waveform to look just like the ‘old green signals and black background’. That’s how I roll, creature of habit. Please pray for Mrs. Miller.

For you companies that keep track of SLOC’s (may I say you are driving your engineers nuts trying to count FPGA lines of code!) I clicked the HDL statistics and the tool gives you the break down and totals for each module. By the way I used this tool without using the help tab at all, I’m one of them, so it is very, very intuitive. I also tried the Code to graphics and automated header template generation. By now I hope you have caught onto my enthusiasm, to be honest I just thought this was going to be another RTL simulator but I see what I have been missing. From now on ‘The FPGA Expert’ is proudly using Active-HDL, and this is not marketeering (Is this a word?). Contact Aldec today for pricing and licensing flexibility, they are very workable and know the FPGA design cycle very well.

More articles by Luke Miller…

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