Simplified Assertion Adoption with SystemVerilog 2012

SystemVerilog as an assertion language improved and simplified with the 2012 version compared to the 2005 version. I recently viewed a webinar on SystemVerilog 2012 by consultant Srinivasan Venkataramanan, who works at CVC Pvt. Ltd. There’s been a steep learning-curve for assertions in the past, and hopefully you’ll feel more comfortable after reviewing this blog or watching the full 61 minute recorded webinar. The webinar is hosted at Aldec, although the material applies to any IC design or verification engineer using SystemVerilog 2012 with assertions.

​Srinivasan Venkataramanan, CVC Pvt. Ltd.

Simple Case Study

Consider a clocked system with two signals, req and sig1:

• When req is asserted, then sig1 should be high
• sig1 should go low once, prior to req de-assert and remain low until req is de-asserted

The same conditions are shown below as a timing diagram:

Only the green waveform for sig1 is a valid response, because it meets all of the requirements.

In SVA 2005 syntax the assertion for these requirements takes 6 lines of code, with comments shown in red:

With SVA 2012 we can choose to write two assertions, one for each requirement instead of a single assertion:

The only missing assertion in SVA 2012 for this case study is to define, “prior to req de-assert and remain low until req is de-asserted”:

The top part of this code fragment is for simulators that support SVA 2012, while the bottom part is pre-2012 code syntax.

This approach in SVA 2012 is edge-wise, which is more intuitive after looking at the timing diagram.

New in SVA 2012

A few new features in the language are listed below, then followed by some examples to better understand the usage.

[TABLE] style=”width: 500px”
|-
| System Function
| Description
|-
| $countbits
| Count the number of 0s, 1s, Xs, Zs
|-
| $assertcontrol
| Controls: LOCK, OFF, KILL, VACUOUSEOFF
|-
| LTL operators
|
|-
| until, until_width, eventually, nextttime, accept_on, reject_on
| Added in 2009
|-

In a simple protocol with Request, Busy and Ready signals the “until” operator is a very compact way to define the proper operation:

Timing Example for the non-overlapping until

Weak vs Strong Sequences

To illustrate the concept of weak and strong sequences consider an example with three signals: start, a, b. I’m looking for start to go active, then signal a, finally two clocks of signal b. A weak sequence for this behavior is shown below and no error message is issued at the end of the simulation period:

Weak Sequence Example

The same behavior as a strong sequence will issue an error at the end of the simulation because the signal b never has a second activation:

Strong Sequence Example

Case Study 2

An ethernet block was introduced to showcase several assertion concepts:

• Asserts – on outputs
• Assumes – on inputs
• Covers – for all port combinations
• Using assertions while building driver BFMs (Bus Functional Models) in UVM (Universal Verification Methodology)

Q&A

Q: Are assertions allowed inside of SystemVerilog classes?
A: Yes, immediate assertions are allowed inside. No, temporal assertions are not allowed inside classes (yet).

Q: My RTL is VHDL, can I still use SVA?
A: Yes, with a simulator like Riviera Pro you can use both languages together. Also, within VHDL 2008 you can write assertions in PSL.

Q: For my RTL code I cannot touch it, can I still add assertions in a separate file?
A: Yes, using the bind feature you can place assertions in a separate file.

Q: Can assertions be used with gate-level netlists?
A: Yes, you can however it will run slowly.

Q: Can we write SVA inside of PSL assertions?
A: Yes, PSL allows this through the V unit.

Q: Can I write assertions for asynchronous events?
A: Yes, SVA supports assertions for both synchronous and asynchronous behavior.

Q: I do my checking with UVM scoreboard, so why should I use SVA?
A: The UVM scoreboard is kind of high-level, while SVA is more low-level, so they are both used together in a complementary manner.

Summary

SVA 2012 is more powerful and intuitive to learn for designers and verification engineers using assertions. Aldec has a simulator called Riviera Pro that supports the new features defined in SVA 2012. View the full webinar here.

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