Wireless Algorithm Validation from System to RTL to Test

This year’s #50DAC will be chock-full of technical content because that is what attracts the masses of semiconductor professionals, like moths to a flame, or like me to a Fry’s Electronics store. Interesting note, I went to high school with Randy Fry. His Dad started the Fry’s supermarket chain which he sold then he went into electronics. That’s why Fry’s Electronics has a similar layout/business model as a grocery store.

Agilent Technologies and Aldec will co-host a technical session on how to validate a digital signal processing algorithm for both floating and fixed point levels. Attendees will gain insight on cross-domain approach to traditional FPGA design flow and learn how to validate FPGA design for leading edge wireless and radar system with a system-level simulation tool integrated into the traditional hardware design flow.

Attendees will gain valuable, practical skills with the following tools and equipment:

• Agilent SystemVue as a programming environment to simulate and verify system performance prior to realizing a dedicated hardware implementation.
• Co-simulation interface with Aldec Riviera-PRO for validation of functional blocks described in SystemVue hardware design library.
• HIL (Hardware in the Loop) to accelerate both design validation and test coverage, saving additional development time.

Date: Wednesday, June 5, 2013
Time: 2:00 PM — 4:00 PM
Location: 17AB
Topic Area: System Level Design and Communication
Speakers:
Dmitry Melnik – Aldec, Inc., Henderson, NV
Sangkyo Shin – Agilent Technologies, Inc., Santa Rosa, CA

The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, electronic design automation (EDA) and embedded systems and software (ESS).

Members are from a diverse worldwide community of more than 1,000 organizations that attend each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives, and researchers and academicians from leading universities.

Close to 300 technical presentations and sessions are selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies.

A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP), embedded systems and design services providers.

The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design.

Some of the highlights of this year’s DAC include:

• Keynotes by industry leaders/visionaries
• Technical Program (panels, special sessions, Designer Track)
• Forums, tutorials, and workshops
• Management Day
• Exhibition Floor
• Colocated Conferences
• Awards for professionals and students

About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com

See Aldec DAC demos HERE.

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