SystemVerilog from Nevada?

When I think of EDA companies the first geography that comes to mind is Silicon Valley because of the rich history of semiconductor design and fabrication, being close to your customers always makes sense. In the information era it shouldn’t matter so much where you develop EDA tools, so there has been a gradual shift to a wider geography. Aldec is one of those early EDA companies that started in 1984, just three years after Mentor opened it’s doors, however Aldec is headquarteredin Nevada instead of Silicon Valley. I wanted to learn more about Aldec tools and decided to watch their recorded webinar on System Verilog.

The first time that I used Aldec tools was back in 2007 when Lattice Semiconductor replaced Mentor’s ModelSim with the Aldec Active-HDL simulator. I updated a Verilog training class and used Active-HDL for my lecture and labs delivered to a group of AEs at Lattice in Oregon. Having used ModelSim before it was actually quite easy for me to learn and use Active-HDL. For larger designs you would use the Aldec tool called Riviera-PRO.

Webinar

Jerry Kaczynski presented the webinar, he’s a research engineer at Aldec, and has been with the company since 1995. His background includes working on simulator standards. With 53 slides in just 65 minutes the pace of the webinar is brisk, and filled with technical examples, no marketing fluff here.

SystemVerilog came about because Verilog ran out of steam in the verification side. Accellera sponsored SystemVerilog and the first standard to extend Verilog in 2005, then by 2009 Verilog and SystemVerilog became merged. SystemVerilog has various audiences:

• SystemVerilog for Design (SVD) – for hardware designers
• SystemVerilog Assertions (SVA) – both design and verification
• SystemVerilog Testbench (SVTB) – mostly verification
• SystemVerilog Application Programming Interface (SV-API) – CAD integrators

SVD
Verilog designers get new features in SystemVerilog like:

• Rich literals: a= ‘1; small_array='{1,2,3,42};
• User-defined data types
• Enumeration types (useful in state machines)
• Logic types (can replace wire and reg)
• Two-value types (bit, int) – simulates faster than 4 state
• New operators (+=, -=, *=, /=, %=, &=, |=, <>=)
• Hardware blocks (always_comb, always_latch, always_ff)
• Implicit .name connections for modules, also implicit .* connections in port list
• Module time (timeprecision, timeunit)
• Conditional statements (unique case, priority keyword – replaces parallel case and full case pragmas)
• New do/while Loop statement
• New break and continue controls

• Simpler syntax for Tasks and Functions
• New procedural block called final
• Aggregate Data Types (Structures, Unions, Arrays – Packed, Unpacked)
• Structures added (like the record in VHDL or C struct)
• Unions added
• Array syntax simplified

• Special unpacked arrays (Dynamic, Associative, Queues) – not synthesizable
• Packages – organize your code better using import

SVA
Assertions are used in property based design and verification, and they look at the design from a functionality viewpoint.

• Look for illegal behavior
• Assumptions on inputs
• Good behavior, coverage goals

• HW designers add assertions in code to document and verify desired behavior
• System level designers can add protocol checkers at top level
• Verification engineers can add verification modules bound to an object to monitor behavior

SV Interfaces
For communicating between modules SV Interfaces bring new abilities and less typing:

SV Testbench

• Class is used for OOP
• Inheritance – reuse previous classes
• Polymorphism – same name do different things depending on class
• Abstract classes – higher level
• Constrained random testing (CRT)
• Spawn threads

• Mailbox (type of Class) – FIFO for message queue
• Functional Coverage – coverage analysis (covergroups, coverpoints, bins)

Verification Methodologies

• Verification Methodology Manual (VMM) – created by Synopsys, both testbench and design as SystemVerilog
• Open Verification Methodology (OVM) – created by Mentor and Cadence, has SV and SystemC testbench with design files in any language
• Universal Verification Methodology (UVM) – created by Accellera to unify VMM and OVM
• Teal/Truss – by Trusster as Open Source HW verification utility and framework in C++ and SV

Q&A
Q: What tools support SVA?
A: SVA is included in Riviera-PRO simulator.

Q: How could I use SystemVerilog in my VHDL testbench?
A: You could bind SystemVerilog as checkers, then connect them to entities or components in VHDL.

Q: What is difference between logic and reg?
A: Logic is more than reg, also used where wire was used.

Q: Can I connect VHDL inside of SystemVerilog?
A: That’s not controlled by a standards body, so it’s tool specific.

Q: Can I synthesize a queue?
A: No, not really today.

Q: How are modports related to assertions?
A: Not directly related, modports used to define directions of interconnect.

Q: Can we execute random in modules?
A: Random is used for classes.

Q: Will associative arrays handle multi-dimensions?
A: not yet.

Q: Good SV books?
A: Depends on if you do design or verification. Many good choices. Design subset – Sutherland’s book. Browse Amazon.com.

Q: Constrained random test generation details?
A: Just an overview today, sorry.

Summary
SystemVerilog gives the designer richer ways to express hardware than Verilog, more clearly defined intent, better verification with assertions, and use fewer lines of code. It’s about time to upgrade from classic Verilog to SystemVerilog in order to reap the benefits. VHDL designers may benefit from using SV for verification.