Big processors get all the love, it seems. It’s natural, since they are highly complex beasts and need a lot of care and feeding in the EDA and fab cycle. But the law of large numbers is starting to shift energy in the direction of optimizing microcontrollers.
I mulled the math in my head for a while. In a world with 7 billion people and a projected 50 billion “connected devices”, there are conservatively speaking at least 40 billion smaller things with powerful microcontrollers inside. That’s not counting the small package, jelly bean MCU parts inside a toaster. I’m talking about 32-bit MCUs powerful enough to drive a networking stack, display, and user interface. Billions and billions, as Carl Sagan used to say.
The same art that has gone into designing high-end microprocessors will turn into designing this new breed of microcontroller, with one big difference: power consumption will rule designs, from beginning to end. The microcontroller world has gotten away predominantly with 99% sleep (something I’ve recently seen referred to as “near death” mode, depressing) and relatively low clock rates as the way to conserve power, but that’s going to change as the expectations for connectivity and performance in these new connected devices shift.
Microcontroller and SoC designs turned to massive clock gating a generation ago as a power management technique, dynamically shutting down logic paths not in use at a particular moment. Clock gating on this scale has been a highly manual art, well worth the investment in a large part. (See the discussion on P. A. Semi in my post on the Apple A5 SoC family.)
A little more than a year ago, Cadence quietly purchased Azuro, proponents of clock concurrent optimization. CCOpt does timing-driven placement, logic re-sizing, and clock gating in a single step, rather than leaving the clock gating to man-months of post-design hand optimization, or considering clock gating separately from timing considerations. They’ve integrated that capability into their Encounter Digital Implementation System 11.1.
Broadcom was one of the first companies to grab the CCOpt capability, but they have looked at it from a performance and timing closure perspective, and as a way to increase EDA design throughput by reducing cycle time. It’s a good first step, and they admit one goal is more performance for the same watts.
When the world’s largest MCU company, Renesas, grabs CCOpt and starts using it, they find something quite interesting as they try to reduce MCU power. Their take is the clock network itself consumes 1/3 of the overall MCU power, even on a relatively pedestrian 160MHz part. By using CCOpt, Renesas teams pulled out a 30% reduction in MCU clock power – that’s around 10% of the overall chip power just by optimizing the clock network.
That doesn’t sound like much, but consider there are cars with upwards of 100 MCUs inside, and many of them are always on managing safety, performance, and environmental systems. Renesas shares their outlook for MCUs in cars, and what power consumption means to them.
Automotive is just one area where advanced MCUs will make an impact. Reducing MCU power as 40 billion devices are more and more in the “on” state will draw increasing amounts of EDA attention in the next few years. We’ll see more love flow from the clock gating and optimization practices for big processors down to MCUs soon.Share this post via: