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ESL Tool Update from #51DAC

ESL Tool Update from #51DAC
by Daniel Payne on 06-24-2014 at 4:13 pm

As promised in my May 27th blog, I visited an ESL company at DAC three weeks ago that introduced two new tools:

  • Thermal Profiler
  • Power Intelligence

Gene Matter from DOCEA Power met with me in their booth to provide the update. The basic premise is that modeling and simulating for power and thermal at the ESL level provides early insight and more benefits than waiting until RTL implementation.

Q&A

Q: So, what’s new this year at Docea Power?

At DAC this year we have a new tool called ThermalProfilerwhich came out of the Ace ThermalModeler tool. There’s a simplified Excel-based thermal model capture tool for all of the 3D geometries, floorplans, materials and heat exchange surfaces.

With most PCB tools you can only take in a package model, however we allow you to start with a chip plan and package model, then generate a compact thermal model (mesh equivalent models). The 3D stackup is used in a package assembly model.

Q: How accurate are these compact therm models?

The compact thermal model can be compared versus another tool like Icepak (ANSYS) and FloTherm (Mentor). They could compare a steady state power comparison, or transient thermal analysis. That comparison confirms the model accuracy.

Q: How fast does your modeling and simulation system run compared to other approaches?

As an example, consider a silicon to substrate connection using a solder ball, where a 3D heat path is modeled and then simulated. Existing CFD tools take hours to create models for this complex structure. With model order reduction we have seen 100-10,000 times speed up in transient analysis whereby the user can now do dynamic analysis to solve power as a function of temp and multiple use cases.

Q: What kind of feedback does your tool provide?

For each block on your chip you can describe the power activity for: processor, memory, graphics, io power, etc. Now what happens in a scenario with different activity? We can solve power as a function of temperature for each chip block or by gate counts, so we know leakage and dynamic power numbers. The thermal limits can be set up across the chip, and I can visualize my simulated power graphically for both spatial (floorplan) and temporal (power/temp over time) data.

We can also import your CFD data, or you can quickly create it. Any stack-up can be built in this tool, then simulated for dynamic real time thermal simulation. You can see power and temperature as a function of time for each scenario on your design before it is fabricated. You can distinguish between leakage and dynamic power usage. This info helps you to place the thermal sensors on a chip for throttle control.

SoC designers may want to throttle device performance in order to stay within thermal limits.

Q: How is ThermalProfiler different than Ace ThermalModeler?

ThermalProfiler complements Ace ThermalModeler because ThermalProfiler does not require you to build a power model.

ThermalProfiler is aimed at designers that want to identify hotspots and measure leakage currents.

A user can swap SoC block positions, or rotate blocks and see the thermal effect.

Q: Who is using ThermalProfiler?

A European company is using ThermalProfiler now and multiple companies are evaluating the product.

Q: What type of engineer would use ThermalProfiler?

Users of ThermalProfiler would be the power architects that need thermal info on a floor plan and design, or a member of the design implementation teams (not a separate thermal or package group). They need to answer the questions – Where do I place my thermal sensors, what is the best floorplan, how do I improve my dynamic thermal and power management policies, is my design at risk for thermal runaway without thermal management?

Q: What is the second new product that you’re announcing?

Our next new front end product is called API – Ace Power Intelligence. It’s a web-based tool to create, manage and maintain a repository of power models. API Allows you to automate the interconnect, voltage and clock tree domains. For an SoC designer they can integrate multiple blocks with their models, annotate the power models as characterization becomes available, or they can use scaling factors, equations or a 3rd party characterization tools. Creating all of these power models and version them, check out and check in the power models. You can specific the clock domain for each block, the voltage domains for blocks. This creates a collaborative engineering environment for power models. This approach then supports a distributed work force. You can mix parameterized models with fixed data, table look ups, equations, etc.

Q: How does API connect with other tools?

API is the front-end for AcePlorer, because it creates the power models.

In the old days you had to create a hierarchical power model for each IP block. Now you can check out each template, assign a power domain, and generate a schematic of the power blocks, voltage domains, clock tree and interconnect.

Q: What are some of the industry trends for power?

The industry would benefit from a common power repository for all commercial IP blocks. The foundries and fabs have IP along with a design kit including power models. What about IP outside of a foundry? Where is the power model? For soft IP what is my power model?

Q: How would you summarize API?

API allows you to quickly create power templates. Users of API would be SoC customers getting internal and external IP and have a large database of IP and power models. Building 20 variations of the same SoC to create a family, you need a way to quickly know the power values.

lang: en_US


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