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Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges

Optimism Prevailed at CEO Outlook, though Downturn Could Bring Unpredictable Challenges
by Nanette Collins on 06-22-2023 at 10:00 am

CEO Outlook #2
CEO Outlook participants, front row (l-r): Niels Faché, John Lee and Prakash Narain; back row (l-r): Scott Seiden, Director Strategic Marketing at Keysight EDA Portfolio, Dean Drako, John Kibarian, Ed Sperling, Bob Smith, Executive Director of the ESD Alliance, Simon Segars and Joe Sawicki. Source: Julie Rogers, Director of Marketing for SEMI Americas and the ESD Alliance

Chances are anyone who attended the CEO Outlook will say it was an engaging, entertaining and enlightening view of the chip design space, though CEO Outlook may be a misnomer as four of the seven panelists had C-Suite titles other than CEO.

Regardless, the collective view was optimistic, though caution prevailed as the economic downturn could bring unpredictable challenges. The discussion was kept on point by moderator Ed Sperling, editor in chief of Semiconductor Engineering. SEMI’s ESD Alliance sponsored the event and it was hosted by Keysight.

As expected, the conversation covered topical subjects like heterogeneous integration, chiplets, education and manufacturing, but continued to drift back to the role AI is playing in the changing industry dynamics. John Kibrarian, President and CEO of PDF Solutions and a member of the ESD Alliance Governing Council, reinforced the role of AI, predicting the semiconductor industry will grow to $1 trillion by 2030 propelled by increasing AI computer needs.

AI’s impact on the design tool market and the industry cannot be overstated, agreed Dean Drako, President and CEO of IC Manage and former Governing Council member, who believes it will help accelerate productivity. It will be both a challenge with the massive amount of data that AI will generate, he warned.

AI puts the industry in an amazing space to monetize what EDA is doing as well as being able to transform the world, allowed Joe Sawicki, Executive Vice President of Siemens EDA and a Governing Council member. AI comes with a host of chip design-related questions that he quickly ticked off –– What if generative AI comes into the design space and how would it be useful or innovative? How would it discover what’s been done? What’s being pulled together in compelling ways? He finished with the promise: “It’s going to be an amazing ride in terms of how we take advantage of these opportunities.”

John Lee, GM and VP at Ansys and a newly elected ESD Alliance Governing Council member, chose a different angle and said heterogenous integration is both an opportunity and a challenge. Multiphysics around 3D ICs is a big challenge and an opportunity. So too are heterogeneous IC designs.

Kibarian took the manufacturing perspective and sees opportunities to improve production flows. He responded to Lee’s comments by adding heterogeneous development systems will lead to manufacturing challenges. The system package makes manufacturing challenging because the value isn’t in the wafer fab and assembly is a challenging process now due in many ways to geopolitics. The test points are much more complex.

Chiplets and the heterogeneous design have physical challenges that could be electromagnetic, thermal or electrothermal, continued Niels Faché, VP and GM at Keysight EDA and a newly elected Governing Council member. While tools are available, it’s critical that they are applied to solve the problems they’re well suited for and integrated in an overall portfolio, he added. Technologies may be available but may need to be modified for chiplets and 3D ICs. They also need to be in an integrated workflow and so they are not going from one highly specialized group to another specialized group causing data transfer problems. Faché’s advice to designers is to make sure they have the right tool for the right job and those tools are integrated in an overall workflow.

At Faché’s mention of chiplets, Sperling turned to Simon Segars, a former member of the ESD Alliance Governing Council, for his insights on the emerging chiplets market. Segars acknowledged the chiplet momentum and the complexity around chip and physical IP, libraries and memories and in-place blocks for chiplet design. He foretells a shift will be required –– a practical way forward once designers are comfortable using chiplets.

Prakash Narain, President and CEO of Real Intent and a Governing Council member, is a verification expert and firmly believes opportunities are available to further automate shift left or moving verification up much earlier in design. Since it’s a design step, the designer must get involved in this process. Due to time pressures, a verification vendor has to create the best experience for success. The challenge is technology innovation and the industry is responding, he affirmed, by investing in technology and innovation to design the user experience while expanding the size of the business space and engineering innovation.

As the discussion wound down, one attendee asked panelists what they would tell top U.S. policy makers, given the chance. Drako jumped in, describing his chance to talk recently to President Biden. “Basically, I made three points,” he said. “One was that we need education in the United States and that we need to invest so that we are top of the world in education because that’s how we’re going to compete in the long run. That’s how we competed over the last 500 years when we invented the first public education system. Second, AI is going to change video surveillance and we need to invest, reinvest as a country in manufacturing.”

Lee perhaps summed up the discussion best by noting that all the challenges the panelists talked about cannot be solved immediately. It takes a village to solve them or the idea of open extensible platforms as a form of a workable model. “SaaS-based systems talking to each other is the future. We have to embrace all this. Then we can solve more of the problems we face.”

The ESD Alliance Membership Drive

‘Tis the membership drive season for the ESD Alliance, an industry organization devoted to promoting the value of the electronic system and semiconductor design ecosystem as a vital component of the global electronics industry. It offers programs that address technical, marketing, economic and legislative issues affecting the entire industry. For more information, visit the ESD Alliance website. Or contact Bob Smith, Executive Director of the ESD Alliance, at bsmith@semi.org or Paul Cohen, ESD Alliance’s Senior Manager, at pcohen@semi.org.

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Also Read:

Nominations for Phil Kaufman Award, Phil Kaufman Hall of Fame Close June 30

SEMI ESD Alliance CEO Outlook Sponsored by Keysight Promises Industry Perspectives, Insights

Cadence Hosts ESD Alliance Seminar on New Export Regulations Affecting EDA and SIP March 28

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