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Parallel-Based PHY IP for Die-to-Die Connectivity

Parallel-Based PHY IP for Die-to-Die Connectivity
by Mike Gianfagna on 09-17-2020 at 10:00 am

Two converging trends for die to die connectivity in MCMs 1

 

Synopsys has released a Technical Bulletin entitled “Parallel-Based PHY IP for Die-to-Die Connectivity”. The piece is authored by Manuel Mota, senior product marketing manager, staff at Synopsys. Manuel has worked at Synopsys for 11 years in the IP area. Prior to that, he worked at MIPS Technologies, Chipidea (acquired… Read More


Making Full Memory IP Robust During Design

Making Full Memory IP Robust During Design
by Daniel Payne on 08-28-2020 at 10:00 am

64Mb SRAM example, memory IP

Looking at a typical SoC design today it’s likely to contain a massive amount of memory IP, like: RAM, ROM, register files. Keeping memory close to the CPU makes sense for the lowest latency and highest performance metrics, but what about process variations affecting the memory operation? At the recent DAC conference held… Read More


ARC Processor Virtual Summit!

ARC Processor Virtual Summit!
by Daniel Nenni on 08-21-2020 at 6:00 am

ARC Processor Virtual Summit 2020

The ARC Processor has a rich history. Originally named the Argonaut RISC Processor, it was designed for the Nintendo Game Systems in the 1990s. Argonaut Technologies Limited later became ARC International. My first intimate exposure to ARC was in 2009 when Virage Logic acquired ARC. A year later Virage was acquired by Synopsys… Read More


Synopsys Webinar: A Comprehensive Overview of High-Speed Data Center Communications

Synopsys Webinar: A Comprehensive Overview of High-Speed Data Center Communications
by Mike Gianfagna on 07-27-2020 at 6:00 am

Screen Shot 2020 07 25 at 8.43.22 PM

High-speed communication is a critical component for many applications, most notably in the data center. The serializer/deserializer physical interface, or SerDes PHY is the backbone of many different forms of high-speed communication for this application. Use cases include on chip, between chips, between boards and racks… Read More


Accelerating High-Performance Computing SoC Designs with Synopsys IP

Accelerating High-Performance Computing SoC Designs with Synopsys IP
by Daniel Nenni on 07-22-2020 at 6:00 am

Synopsys DesignWare IP

Semiconductor IP is one of the most talked about topics on SemiWiki. Always has been, always will be. Synopsys is also one of the most talked about topics on SemiWiki and IP is a very big part of that, absolutely.

After reading Eric Esteve’s latest IP Report I Googled around and found some interesting things. First, I found a Brief HistoryRead More


Quantifying the Benefits of AI in Edge Computing

Quantifying the Benefits of AI in Edge Computing
by Bernard Murphy on 07-21-2020 at 6:00 am

Architectures for Edge computing

Many of us are now somewhat fluent in IoT-speak, though at times I have to wonder if I’m really up on the latest terminology. Between edge and extreme edge, fog and cloud, not to mention emerging hierarchies in radio access networks – how this all plays out is going to be an interesting game to watch. Ron Lowman, DesignWare IP Product… Read More


Synopsys Introduces Industry’s First Complete USB4 IP Solution

Synopsys Introduces Industry’s First Complete USB4 IP Solution
by Mike Gianfagna on 06-15-2020 at 6:00 am

USB 4 Connector source Intel

Synopsys announced an addition to its popular DesignWare IP portfolio recently that has some significant ramifications. The company announced the industry’s first complete USB4 IP solution. Before we get into the details of the announcement, let’s take a quick look at the USB standard and why it’s important.

Standards… Read More


Synopsys – Turbocharging the TCAM Portfolio with eSilicon

Synopsys – Turbocharging the TCAM Portfolio with eSilicon
by Mike Gianfagna on 04-27-2020 at 10:00 am

Screen Shot 2020 04 18 at 2.21.03 PM

About 90 days ago, Synopsys completed the acquisition of certain IP assets from eSilicon. The remaining entirety of eSilicon was acquired by Inphi Corporation. I was the VP of marketing at eSilicon during that acquisition so it’s very interesting to me to find out how things are going with those certain IP assets.  I got an opportunity… Read More


Synopsys is Changing the Game with Next Generation 64-Bit Embedded Processor IP

Synopsys is Changing the Game with Next Generation 64-Bit Embedded Processor IP
by Mike Gianfagna on 04-07-2020 at 6:00 am

ARC HS5x HS6x block diagram

Synopsys issued a press release this morning that has some important news – Synopsys Introduces New 64-bit ARC Processor IP Delivering Up to 3x Performance Increase for High-End Embedded Applications. At first glance, one could assume this is just an announcement for some new additions to the popular ARC processor family. While… Read More


Security in I/O Interconnects

Security in I/O Interconnects
by Mike Gianfagna on 03-25-2020 at 10:00 am

shutterstock 1221815029

I got a chance to chat with Richard Solomon at Synopsys recently about a very real threat for all of us and what Synopsys is doing about it. No, the topic isn’t the Coronavirus, it’s one that has been around a lot longer and will continue to be a very real threat – data and interconnect security.

First, a bit about Richard. He is the technical… Read More