CES 2020 is being held this week in Las Vegas with over 4,500 exhibiting companies and over 175,000 attendees. The show includes a broader industry than just electronics, which led to it being renamed CES (previously the Consumer Electronics Show) and the sponsoring organization changing its name from the Consumer Electronics… Read More
IEDM 2019 – Applied Materials panel EUV Recap
On Tuesday night of IEDM, Applied Materials held a panel discussion “The Future of Logic: EUV is Here, Now What?”. The panelists were: Regina Freed, managing director at Applied Materials as the moderator, Geoffrey Yeap, senior director of advanced technology at TSMC, Bala Haran, director of silicon process research at IBM, … Read More
Cadence Continues Photonics Industry Engagement
On November 13, Cadence held its annual Photonics Summit. Cadence has been hosting this event for several years with the intention of advancing the photonics industry. With this event, Cadence has been a catalyst in furthering photonic product development. It’s quite remarkable that Cadence hosts such an event in a field where… Read More
IEDM 2019 Press Lunch Exposed!
One of the many benefits of blogging for SemiWiki is the free conference passes and buffet lunches, absolutely. IEDM is one of the more prestigious semiconductor conferences, now in its 65th year, is being held at the Hilton Hotel in San Francisco’s famed Union Square this week. This year more than 1,910 semiconductor professionals… Read More
WEBINAR: Analyzing PowerMOS Devices to Reduce Power Loss and Improve Reliability
The symbol for a PowerMOS device in a converter circuit schematic looks simple enough. However, it belies a great deal of hidden complexity. A single device is actually a huge array of parallel intrinsic devices connected together to act as a single high power device. While their gate lengths are small, as with many other MOS devices,… Read More
Webinar on coping with the complexities of 3D NAND design
In order to beat Moore’s Law NAND Flash memories have moved from a planar topology to 3D construction. This allows for increased memory sized in much the same way a multistory building provides more building square footage on the same size building lot. Just like in building construction, adding a third dimension to the mix increases… Read More
Webinar Recap: IP Security Threats in your SoC
Three years ago my youngest son purchased a $17 smart watch on eBay, but then my oldest son read an article warning about how that watch would sync with your phone, then send all of your contact info to an address in China. My youngest son then wisely turned the watch off, and never used it again. Hackers have been able to spoof and hide … Read More
Where has the ASIC Business Gone?
As the traditional ASIC business disappears before our eyes with the recent divestitures and acquisitions, I have been asking questions amongst the fabless semiconductor ecosystem and am getting few answers.
Who or what is going to step in to enable start-ups and new to silicon systems companies with application specific chips?… Read More
Top Three Reasons to Attend the Synopsys Fusion Compiler Event!
As a professional semiconductor event attendee I can pretty much tell if an event will be successful by looking at the agenda. What I look for is simple, customer presentations. Not company presentations or partner presentations but actual customer case studies presented by name brand companies. For this event Google, Intel,… Read More
WEBINAR REPLAY: AWS (Amazon) and ClioSoft Describe Best Cloud Practices
ClioSoft has been working with the leading cloud computing providers running experiments on various EDA cloud architectures for a while now. One example of that was a project with Google I previously wrote a blog about, For EDA Users: The Cloud Should Not Be Just a Compute Farm. Since then, ClioSoft has also teamed up with Amazon … Read More
Facing the Quantum Nature of EUV Lithography