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Cadence Summit Highlights Automotive Market Dynamics and System Enablement

Cadence Summit Highlights Automotive Market Dynamics and System Enablement
by Camille Kokozaki on 12-04-2018 at 12:00 pm

Cadence held a well-attended Automotive Summit where Cadence presented an overview of their solution and system enablement along with industry experts and established or startup companies sharing their perspective and product features from autonomous driving, LiDAR, Radar, thermal imaging, sensor imaging, and AI.… Read More


Webinar: Turnkey Bluetooth True Wireless Stereo Earbuds and Speakers

Webinar: Turnkey Bluetooth True Wireless Stereo Earbuds and Speakers
by Bernard Murphy on 12-01-2018 at 7:00 am

When we were first introduced to earbuds, in-ear speakers connected through thin wires to your phone (and earlier portable music devices), they seemed pretty convenient for private entertainment at work, while walking, exercising, doing almost anything. Until we started to realize those long dangly wires weren’t ideal. They’d… Read More


Security and RISC-V

Security and RISC-V
by Bernard Murphy on 11-30-2018 at 7:00 am

One of the challenges in the RISC-V bid for world domination may be security. That may seem like a silly statement, given that security weaknesses are invariably a function of implementation and RISC-V doesn’t define implementation, only the instruction-set architecture (ISA). But bear with me. RISC-V success depends heavily… Read More


Is IP SoC 2018 Still Alive? Better than Ever!

Is IP SoC 2018 Still Alive? Better than Ever!
by Eric Esteve on 11-27-2018 at 12:00 pm

The 21[SUP]st[/SUP] IP-SoC Days conference will be held in Grenoble, France, on December 5-6, 2018. IP-SoC is now the unique IP centric conference, with presentations reflecting the complete IP ecosystem: IP suppliers and foundries, external IP or internal reuse managers. Look at the program, you will see the hot topics covered… Read More


DAC 2019 to Host the Second System Design Contest!

DAC 2019 to Host the Second System Design Contest!
by Daniel Nenni on 11-13-2018 at 7:00 am

Interested in showing off your talent in developing deep learning algorithms on embedded hardware platforms for solving real-world problems? Join the second System Design Contest (SDC) at the 56[SUP]th[/SUP] Design Automation Conference in 2019!… Read More


Webinar: NVIDIA Talks High Quality Metrics in Power Integrity Signoff

Webinar: NVIDIA Talks High Quality Metrics in Power Integrity Signoff
by Bernard Murphy on 11-09-2018 at 12:00 pm

There’s a familiar saying that you can’t improve what you can’t measure. Taking that one step further, the more improvement you want, the more accurately you have to measure. This become pretty important when you’re building huge designs in advanced technologies. Margins are a lot tighter all round and use-cases are massively… Read More


Is ARM TechCon Really Worth it?

Is ARM TechCon Really Worth it?
by Daniel Nenni on 11-05-2018 at 6:00 am

The ARM TechCon organizers are asking me what I thought of this year’s conference so here it goes. As you know I am a big fan of ARM TechCon and feel it is one of the better conferences for SoC design. This year however I noticed a big change in demographics. Maybe the location change had something to do with it but I definitely saw different… Read More


The Latest from Samsung Semiconductor

The Latest from Samsung Semiconductor
by Tom Dillinger on 10-29-2018 at 12:00 pm

Earlier this Spring, Samsung Foundry held a technology forum, describing their process roadmap and supporting ecosystem developments (link). Recently, the larger Samsung Semiconductor organization conducted a Tech Day at their campus in San Jose, presenting (and demo-ing) a broader set of products. The focus of the day was… Read More


Essential Analog IP for 7nm and 5nm at TSMC OIP

Essential Analog IP for 7nm and 5nm at TSMC OIP
by Tom Simon on 10-24-2018 at 7:00 am

When TSMC’s annual Open Innovation Platform Exposition takes place, you know it will be time to hear about designs starting on the most advanced nodes. This year we were hearing about 7nm and 5nm. These newer nodes present even more challenges than previous nodes due to many factors. Regardless of what kind of design you are undertaking… Read More


The Latest in Parasitic Netlist Reduction and Visualization

The Latest in Parasitic Netlist Reduction and Visualization
by Tom Dillinger on 10-22-2018 at 12:00 pm

The user group events held by EDA companies offer a unique opportunity to hear from designers and CAD engineers who are actually using the EDA tools “in the trenches”. Some user presentations are pretty straightforward – e.g., providing a quality-of-results (QoR) design comparison when invoking a new tool feature added to a recent… Read More