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Webinar 800x100 (1)
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What’s new with HSPICE at DAC?

What’s new with HSPICE at DAC?
by Daniel Payne on 06-18-2012 at 5:50 pm

One year ago I met with Hany Elhak of Synopsys to get an update on what was new with HSPICE in 2011, so this year at DAC Hany met me at the Synopsys booth for a quick update.

HSPICE has something called Precision Parallel so with 16 cores your IC circuit simulations will have about 10 x speed up compared to a single core.… Read More


Virtual Platforms plus FPGA Prototyping, the Perfect Mix

Virtual Platforms plus FPGA Prototyping, the Perfect Mix
by Paul McLellan on 06-03-2012 at 8:59 pm

There are two main approaches to building a substructure on which to do software development and architectural analysis before a chip is ready: virtual platforms and FPGA prototyping.

Virtual platforms have the advantage that they are fairly quick to produce and can be created a long time before RTL design for the various blocks… Read More


Synopsys Update 2012!

Synopsys Update 2012!
by Daniel Nenni on 05-28-2012 at 10:22 am

Synopsys just delivered second quarter 2012 results with improved revenue on a year-over-year basis. Unfortunately operating expenses are said to be out of control. I’m not a stock guy so for more financial information and analysis try the Motley Fool article HERE.

The interesting thing to note is that Synopsys still has a pile… Read More


Semiconductor Ecosystem Keynotes: ARM 2012

Semiconductor Ecosystem Keynotes: ARM 2012
by Daniel Nenni on 05-17-2012 at 5:00 pm

Yesterday’s SEMICO IP Ecosystem Conference was well worth the time. Everybody was there: ARM, Synopsys, Cadence, Mentor Graphics, GlobalFoundries, TSMC, MIPS, Tensilica, AMD, Atrenta, Sonics, and Tabula, everybody except Intel of course. What do Intel and I have in common? We don’t play well with others…

First up was… Read More


IC design at 20nm with TSMC and Synopsys

IC design at 20nm with TSMC and Synopsys
by Daniel Payne on 05-02-2012 at 10:25 am

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While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.… Read More


Synopsys Users Group 2012 Keynote: Dr Chenming Hu and Transistors in the Third Dimension!

Synopsys Users Group 2012 Keynote: Dr Chenming Hu and Transistors in the Third Dimension!
by Daniel Nenni on 04-08-2012 at 7:00 pm

It was an honor to see DR. Chenming Huspeak and to learn more about FinFets, a technology he has championed since 1999. Chenming is considered an expert on the subject and is currently a TSMC Distinguished Professor of Microelectronics at University of California, Berkeley. Prior to that he was the Chief Technology Officer of TSMC.… Read More


Synopsys Users Group Silicon Valley 2012 Keynote: ARM

Synopsys Users Group Silicon Valley 2012 Keynote: ARM
by Daniel Nenni on 03-28-2012 at 12:49 pm


Keynote #2 at SNUG 2012 was John Cornish, VP Marketing at ARM. Why they sent a marketing person to speak in front of 2,000+ engineers I do not know. To top that, next time they should send a sales person and do a real dog and pony show. To find out more about John I checked his LinkedIn profile which was bare. So enough about John, lets hit … Read More


Synopsys Users Group Silicon Valley 2012 Keynote: Aart de Geus

Synopsys Users Group Silicon Valley 2012 Keynote: Aart de Geus
by Daniel Nenni on 03-27-2012 at 1:26 pm

SNUG Chairman John Busco opened the session with a few words about Aart de Geus, the silver anniversary of Synopsys, and some SNUG statistics. A whopping 2,500 people registered this year! Probably due to the Magma acquisition which is prominently displayed on “Welcome Magma Users” signs and on the flat screens which are everywhere.… Read More


Synopsys Validates EDA360?

Synopsys Validates EDA360?
by Daniel Nenni on 03-26-2012 at 4:26 pm

Before I get too snarky here, I would like to thank Synopsys for the invitation to SNUG 2012 and including me with the professional editors at a 75 minute roundtable discussion with Synopsys CEO Aart de Geus. While Aart is not my favorite big EDA CEO (Wally Rhines of Mentor bought me lunch and returns my email), he is definitely the most… Read More