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How many 28nm FDSOI SoC Design Starts in 2015? In 2020?

How many 28nm FDSOI SoC Design Starts in 2015? In 2020?
by Eric Esteve on 11-13-2014 at 4:28 am

I would like to further discuss this graphic (presented during IP-SoC 2014 by John Koeter, VP of Marketing IP and prototyping, Synopsys) and focus on Active Design and Tapeouts at 28nm. In fact the very first activity appeared in Q1 2007, but it was only during 2010 that 28nm become popular, after the first Tapeouts coming in Q1 and an average number of active designs per quarter being around 75, to climb to 100 ranges during 2011 and 2012. To really understand this graphic we need to remember that the active design and Tapeouts numbers stop being reported in the graphic, but still exists in the real life! These numbers may still grow, and considering the 28/32nm shape, I would guess so. As you know, before going into production, an IC passes through active design (18 to 24 months), then Tapeout/prototyping/validation (another 6 to 12 months) before production ramp-up and full production. In other words, the active designs listed in Q4 2012 are most probably not yet into production today!


The next graphic (presented by Handel Jones from IBS at the Shanghai SOI forum last September) represent the volume production wafer for the same 28nm technology node. This node is in full production for a couple of years, but you can see that IBS forecast that a higher wafer count will be in production in 2024 than next year in 2015! That means that 28nm will be the mainstream node for years, and we know the reasons: NRE cost far too high for 20nm and lower, and $/transistor cost inversion starting at 14/16nm. At least for a SoC design, integrating multiple CPU, memory and many IP, this 28nm node will be the best development cost/area/power compromise. If we consider the licensing agreement signed by Samsung for FD-SOI technology with ST-Microelectronics, starting at 28nm, we can expect higher design start count in 2015 than before on 28nm FD-SOI, as well as on the various 28nm flavors.


You may be convinced that 28nm will stay the mainstream node for years, but wondering why 28nm FD-SOI should be used to support mainstream applications? In fact, we should look at FD-SOI unique value proposition, and extract the key arguments:

  • Wafer cost: SOI wafer processing need less mask levels (ion implants), compensating the current raw wafer overcost. When this overcost will decrease, due to higher SOI wafer consumption, the wafer final cost may be lower than for 28nm bulk.
  • Performance (Processor and digital logic) can be 30% better than bulk, thanks for the forward bias capability.
  • SRAM/TCAM deliver better performance and less power than nulk.
  • Analog & High Speed (SerDes for example) deliver better performance than bulk, and even more important, less variability.
  • Ultra Low voltage capability, unique to Fd-SOI, allow designing far better power efficient devices to address mobile applications and Internet of Things IC.


Does it means that FD-SOI will canibalize 28nm node? No and there will be various 28nm derivatives and possible shrink, but this FD-SOI option will become more and more attractive in the future, as soon as a real IP ecosystem will become available. Don’t forget that one of the semiconductor giant is already supporting the technology, attracting the first IP vendors (like Cadence supporting DDR4 memory controller IP on 28 FD-SOI) and we can guess that some IP design teams are working to fill the needs of Samsung or Samsung’s customers.

How many 28nm FD-SOI design starts in 2020? When and if the technology reach the mainstream IC design enterprises (most of them being located in China at that time), we can expect to count many more design starts in 2020 than in 2015, simply because 28nm should still be the mainstream technology node for cost-efficient SoC, and FD-SOI will have demonstrated the performance and power advantages on Silicon, and even more important in power-aware systems. It’s likely that doing evanlegization in China will be necessary, the discussion I had with Mark Ma during IP-SoC 2014 in Grenoble show that curiosity for FD-SOI is here, it will be time to further explain (again and again) why FD-SOI is Faster, Cooler and Cheaper.

From Eric Esteve from IPNEST

More Article From Eric Esteve


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