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Palladium Moves Power (and Temperature) Modeling to the System Level

Palladium Moves Power (and Temperature) Modeling to the System Level
by Bernard Murphy on 12-13-2015 at 12:00 pm

I had a debate with Steve Carlson of Cadence earlier in the year at the EDPS conference on whether there were really any truly effective solutions for doing power estimation in emulation. I thought there weren’t and he said I was wrong. After attending the Cadence front-end summit last week, I have to admit he has a point.

First, who… Read More


Cadence Enters the RTL Power Estimation Game

Cadence Enters the RTL Power Estimation Game
by Bernard Murphy on 12-09-2015 at 12:00 pm

At the Cadence front-end summit last week, Jay Roy presented the Cadence Joules solution for RTL (and gate-level) power estimation. Jay is ex-Apache, so knows his way around RTL power estimation which should make Joules a product to watch. Joules connects very natively to Palladium for power characterization for realistic software… Read More


Optimizing power for wearables

Optimizing power for wearables
by Bernard Murphy on 12-06-2015 at 4:00 pm

I was at the Cadence front-end summit this week; good conference with lots of interesting information. I’ll start with a panel on optimizing power for wearables. Panelists were Anthony Hill from TI, Fred Jen from Qualcomm, Leah Clark from Broadcom and Jay Roy from Cadence. Panels are generally most entertaining when the panelists… Read More


Globalfoundries 22FDX Technology Shows Advantages in PPA over 28nm Node

Globalfoundries 22FDX Technology Shows Advantages in PPA over 28nm Node
by Tom Simon on 11-20-2015 at 7:00 am

I really enjoy ARM Techcon when it rolls around every year because it has such a wide range of topics and exhibits. You can find maker gadgets, IoT information, small boards for industrial control, software development kits, semiconductor IP vendors as well as the big EDA players and foundries. This year after perusing the exhibit… Read More


Maybe Clockless Chip Design’s Time has Come

Maybe Clockless Chip Design’s Time has Come
by Tom Simon on 11-16-2015 at 4:00 pm

There have always been novel technologies vying to compete with conventional design practices. It is hit or miss on the success of these ideas. In the 90’s I recall speaking to someone who was convinced that they could effectively build computers based on multilevel logic. This, as we know did not pan out. But there have been many … Read More


A (R)evolution in Hardware-based Simulation Acceleration

A (R)evolution in Hardware-based Simulation Acceleration
by Tom Dillinger on 11-16-2015 at 9:45 am

The most exciting products in our industry are those that are both evolutionary and revolutionary. Cadence has just announced an update to their hardware simulation acceleration platform – Palladium Z1 – which continues the evolution of the unique capabilities of processor-based acceleration, plus a revolutionary approach… Read More


Our Own Cadence Amongst the Best Multinational Workplaces!

Our Own Cadence Amongst the Best Multinational Workplaces!
by Daniel Nenni on 10-15-2015 at 12:00 pm

There were some very happy faces around MemCon this week for a variety of reasons. Paul McLellan was smiling because he now works full time for Cadence and has the best medical benefits ever and of course I was smiling because there was free food! … Read More


Wafer-Level Chip-Scale Packaging Technology Challenges and Solutions

Wafer-Level Chip-Scale Packaging Technology Challenges and Solutions
by Tom Dillinger on 10-15-2015 at 7:00 am

At the recent TSMC OIP symposium, Bill Acito from Cadence and Chin-her Chien from TSMC provided an insightful presentation on their recent collaboration, to support TSMC’s Integrated FanOut (InFO) packaging solution. The chip and package implementation environments remain quite separate. The issues uncovered in bridging… Read More


IMEC and Cadence Disclose 5nm Test Chip

IMEC and Cadence Disclose 5nm Test Chip
by Scotten Jones on 10-09-2015 at 7:00 am

Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.

First off Vassilios really… Read More


Cadence Outlines Automotive Solutions at TSMC OIP Event

Cadence Outlines Automotive Solutions at TSMC OIP Event
by Tom Simon on 10-08-2015 at 12:00 pm

I used to joke that my first car could survive a nuclear war. It was a 1971 Volvo sedan (142) that was EMP proof because it had absolutely no semiconductors in the ignition system, just points, condensers and a coil. If you go back to the Model T in 1915 you will see that the “on-board electronics” were not that different. However, today’s… Read More