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IoT Designs Beginning to Shift to 7nm: Promises Upside for Cadence Physically-Aware Design Flow

IoT Designs Beginning to Shift to 7nm: Promises Upside for Cadence Physically-Aware Design Flow
by Mitch Heins on 01-29-2018 at 12:00 pm

Until recently, ICs at bleeding edge nodes like 7nm technology from foundries like TSMC were mostly targeted for high-performance-computing (HPC) and mobile applications or possibly high radix switches that needed the increased performance of advanced nodes. The momentum of Moore’s law and Moore-than-Moore saw foundries… Read More


Simulation and Formal – Finding the Right Balance

Simulation and Formal – Finding the Right Balance
by Bernard Murphy on 01-23-2018 at 7:00 am

Simulation dominates hardware functional verification today and likely will continue to dominate for the foreseeable future. Meanwhile formal verification, once thought to be a possible challenger for the title, has instead converged on a more effective role as a complement to simulation. Formal excels at finding problems… Read More


Scoreboard and Issues Management Tools for PCB Projects

Scoreboard and Issues Management Tools for PCB Projects
by Tom Dillinger on 01-16-2018 at 12:00 pm

The complexity of an SoC design necessitates that the project managers have accurate visibility into the overall design status, spanning the entire range of tasks – from functional simulation error triage, to physical layout verification errors, to electrical analysis results. Flow scripts used by SoC teams parse the log file… Read More


Blurring Boundaries

Blurring Boundaries
by Bernard Murphy on 12-05-2017 at 7:00 am

I think most of us have come to terms with the need for multiple verification platforms, from virtual prototyping, through static and formal verification, to simulation, emulation and FPGA-based prototyping. The verification problem space is simply too big, in size certainly but also in dynamic range, to be effectively addressed… Read More


The Practice of Low Power Design

The Practice of Low Power Design
by Bernard Murphy on 11-14-2017 at 7:00 am

For any given design objective, there is what we in the design automation biz preach that design teams should do, and then there’s what designs teams actually do. For some domains, the gap between these two may be larger than others, but we more or less assume that methodologies which have been around for years and are considered to… Read More


TSMC EDA 2.0 With Machine Learning: Are We There Yet ?

TSMC EDA 2.0 With Machine Learning: Are We There Yet ?
by Alex Tan on 11-06-2017 at 7:00 am

Recently we have been swamped by news of Artificial Intelligence applications in hardware and software by the increased adoption of Machine Learning (ML) and the shift of electronic industry towards IoT and automobiles. While plenty of discussions have covered the progress of embedded intelligence in product roll-outs, anRead More


Photonics Summit Delivers High-Bandwidth Discussion on State of Silicon Photonics

Photonics Summit Delivers High-Bandwidth Discussion on State of Silicon Photonics
by Mitch Heins on 10-03-2017 at 12:00 pm

On September 6, 2017, Cadence Design Systems, Lumerical Solutions and PhoeniX Software hosted their second Photonics Summit. As with last year’s summit, this was a two-day event, with the first day including in a myriad of photonics presentations and the second day being a hands-on workshop. The hands-on workshop taught attendees… Read More


Design for Manufacturability Analysis for PCB’s

Design for Manufacturability Analysis for PCB’s
by Tom Dillinger on 09-29-2017 at 7:00 am

Chip designers are familiar with the additional physical design checking requirements that were incorporated into flows at advanced process nodes. With the introduction of optical correction and inverse lithography technology applied during mask data generation, and with the extension of a 193nm exposure source to finerRead More


High-Speed Equivalence Checking

High-Speed Equivalence Checking
by Bernard Murphy on 09-28-2017 at 7:00 am

Following on product introductions for simulation and prototyping, physical verification and implementation earlier in the year, Anirudh Devgan (Exec VP and GM at Cadence), the king of speed and parallelism has done it again, this time with logic equivalence checking (LEC). Cadence recently announced an advance to their well-known… Read More