WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 588
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 588
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
            
14173 SemiWiki Banner 800x1001
WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 588
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 588
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)

Meeting the Challenges of National Defense Strategy

Meeting the Challenges of National Defense Strategy
by Alex Tan on 03-30-2018 at 7:00 am

21398-fig1.jpgIn February this year, the Department of Defense (DoD) submitted a $686.1 billions budget for 2019 and published a National Defense Strategy outlining the overall spending for defense and military programs. The recently signed US $1.3 trillion spending bill included part of the funding. According to DoD Defense Budget Overview document, the increase in defense related program is anticipated to gradually increased over the next five years (refer to fig. 1).

As illustrated in fig. 2, the strategic approach of DoD is to expand competitive space by means of having creative operating concepts, interoperability, accelerate cycle of innovation and revitalize alliances and new partners.

21398-fig1.jpgAs a solution provider, Cadence has a strong presence in the defense sponsored programs and has established good relationships with relevant parties in both congressional and the DoD ecosystem. Cadence’s active participations in DARPA programs such as CRAFT (Circuit Realization At Faster Timescales), CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) and ACT (Arrays at Commercial Timescales) are some notable examples. Cadence holds a DoD Facility Security Clearance, offers “cleared” engineering resources and maintains commercial relationships with virtually every company that designs or provides electronics to the DoD. Cadence ability to leverage commercial best practices within the confines and requirements of national defense has been key to its success in navigating through its continuous evolution. In the public research domain, over 250 US universities (over a thousand worldwide) have also participated in Cadence Academic Network program, which exposes roughly thirty thousands students annually with best industry practices and design technology.

Cadence Solution and Enablement Strategy21398-fig1.jpg
With its design automation tools, semiconductor IP and solution flows, Cadence has systems design enablement comprising of three tenets:
-Acquire internal expertise on end markets requirements.
-Work directly with leading systems companies in developing products.
-Partner with other industry leaders to provide comprehensive solutions.

System Prototyping and Digital Twin
Catching a glimpse into the DoD Defense Budget Overview details, it stated that “Prototyping and experimentation should be used prior to defining requirements and commercial-off-the-shelf systems… A rapid, iterative approach to capability development will reduce costs, technological, obsolescence, and acquisition risk.” Along this line, the concept of digital twin which refers to a digital replica of a physical product can be applied. The digital twin captures a complete digital footprint of a product from design and development through the end of the product life-cycle. The basic elements of a digital twin for electronics include the physical electronic system in real space, the system prototypes in emulation space and data connections that tie the virtual and real systems together. The success of digital twin relies upon mission data collection and transmission to the digital twin. Hence, proper boundary conditions and capture of the mission profiles and environmental characteristics is crucial in order to prevent unintentional blocking of critical insights potentially needed to improve system efficacy or to avoid field failures. To support this, Cadence offers an array of electronics systems development program execution including:

– Common environment for chip, package and board for system development.
– Incremental parasitic extraction while physical layout progresses.
– Tools with foundry approved signoff engines yielding fewer iterations.
– Utilize metric driven verification methodology that tracks sign-off progress.
– Integrated hardware and software development to reduce integration time.
– Support to industry proven IPs to speed design cycle and to lower costs.

21398-fig1.jpg
Early prototyping is also necessary to prevent surprises. The focus of system function, size, weight and power are the measured metrics. Cadence has developed a new and improved system prototyping methodology that folded-in emulation and analysis steps as well as an explicit go/no-go step prior to committing an idea to do a downstream, physical prototyping step. Emulation provides capacity, accuracy, performance and link to physical analysis. It enables running application software on hardware designs resident to the emulator. Cadence Palladium Z1 Enterprise Emulation Platform provides the enterprise-level reliability and scalability to accelerate system verification at different levels (IPs,subsystems, chips).

Hardware System Co-design
Taking further note from the DoD document: “Platform electronics and software must be designed for routine replacement instead of static configurations that last more than a decade… will realign incentive and reporting structures to increase speed of delivery, enable design tradeoffs in the requirements process,..

Within this context, traditional design implementation involves approach that are segmented (e.g., chip, package, PCB). Such disjointed development is normally yielding a subpar result. With Cadence Virtuoso System Design Platform design team could perform co-design and co-analyze across different domains. It saves time and efforts while producing higher performance and cost competitive systems. For example in today analog and RF designs, failing to account for PCB or package level validation will result in great chance of chip failure. With Virtuoso such system level assessment can be done prior to chip completion.

The new National Defense Strategy provides challenging guidelines to revamp national defense programs and reiterates the impacts of rapid technological advancements to the security environment. According to DoD, the technological advantage depends on a healthy and secure innovation base that includes both traditional and non-traditional defense partners. It continues to streamline processes so that new entrants and small-scale vendors can provide cutting-edge technologies. Cadence has been a direct performer on several DoD projects, collaborated with many DoD suppliers and can act as a key partner to meet the demanding requirements in the agenda. For more details of such engagements and Cadence solutions, please refer to this whitepaper HERE.

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.