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Layout-based ESD Checking Methodology at Nvidia

Layout-based ESD Checking Methodology at Nvidia
by Daniel Payne on 10-14-2013 at 12:43 pm

The company Nvidiais synonymous with designing all things video and GPU, so I watched Ting Ku, director of engineering at an archived webinar today talk about: Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Macro-level Dynamic Solutions.… Read More


ST Endorses PowerArtist with ARM Cores & FDSOI libs

ST Endorses PowerArtist with ARM Cores & FDSOI libs
by Pawan Fangaria on 10-01-2013 at 12:00 pm

It was an interesting webinar I attended, presented by STMicroelectronicson how they are benefited in power saving and thermal dissipation by using FDSOI technology and also by using PowerArtist in their design. So, it’s an advantage from both sides – semiconductor technology and semiconductor design tool. It’s worth attending… Read More


Low-Power Design Webinar – What I Learned

Low-Power Design Webinar – What I Learned
by Daniel Payne on 09-02-2013 at 7:00 pm

You can only design and optimize for low-power SoC designs if you can actually simulate the entire Chip, Package and System together. The engineers at ANSYS-Apachehave figured out how to do that and talked about their design for power methodology in a webinar today. I listened to Arvind Shanmugavel present a few dozen slides and… Read More


Reliability sign-off has several aspects – One Solution

Reliability sign-off has several aspects – One Solution
by Pawan Fangaria on 09-01-2013 at 5:00 pm

Here, I am talking about reliability of chip design in the context of electrical effects, not external factors like cosmic rays. So, the electrical factors that could affect reliability of chips could be excessive power dissipation, noise, EM (Electromigration), ESD (Electrostatic Discharge), substrate noise coupling and… Read More


Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications

Low-Power Design Analysis and Optimization for Mobile and High-Performance Computing Applications
by Daniel Payne on 08-23-2013 at 7:36 pm

For several decades now consumers like me have enjoyed using mobile devices including:

  • Transistor radios, my first one had just 6 discreet transistors in the 1960’s
  • HP 21 Calculator, used in college with Reverse Polish Notation, circa 1976
  • Zenith Data Systems laptop, with two floppy drives, 1980’s
  • Palm Pilot V,
Read More

An EDA Acquisition that Worked

An EDA Acquisition that Worked
by Daniel Payne on 08-14-2013 at 5:30 pm

I first heard about Andrew Yang back in 1993 when he founded a Fast SPICE company called Anagram, then acquired by Avant! in 1996. Andrew’s latest EDA company Apache Design, Inc.was started in 2001, then acquired by ANSYS in 2011. Most EDA mergers simply don’t work because of one or more reasons, like:

  • Incompatible
Read More

RTL Design For Power

RTL Design For Power
by Daniel Payne on 08-11-2013 at 2:25 pm

My Samsung Galaxy Note II lasts about two days on a single battery charge, which is quite the improvement from the Galaxy Note I with only a one day battery charge. Mobile SoCs are being constrained by battery life limitations, and consumers love longer-laster devices.

There are at least two approaches to Design For Power:

  • Gate-level
Read More

Robust Design <- Robust Flow <- Robust Tools

Robust Design <- Robust Flow <- Robust Tools
by Pawan Fangaria on 08-10-2013 at 6:00 pm

I could have written the sequence of the title in reverse order, but no, design is the one which initiates the need of a particular flow and the flow needs support of EDA tools to satisfy that need. It’s okay if the design is small; some manual procedures and workarounds/scripts may be able to perform certain jobs. However, as the design… Read More


Power and Reliability Sign-off – A must, but how?

Power and Reliability Sign-off – A must, but how?
by Pawan Fangaria on 07-29-2013 at 11:00 am

At the onset of SoCs with multiple functionalities being packed together at the helm of technologies to improve upon performance and area; power, which was earlier neglected, has become critical and needs special attention in designing SoCs. And there comes reliability considerations as well due to multiple electrical and … Read More


Efficient Power Analysis and Reduction at RTL Level

Efficient Power Analysis and Reduction at RTL Level
by Pawan Fangaria on 07-22-2013 at 12:30 am

It’s a classic and creative example of design and EDA tool community getting together, exploiting tool capabilities and developing flows which add value to all stake holders including the end consumer. We know power has become extremely important for battery life in smart phones, high performance servers, workstations, notebooks… Read More