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WIKI Multi FPGA Design Partitioning 800x100 
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Aldec
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An FPGA Design Flow with Aldec Tools

An FPGA Design Flow with Aldec Tools
by Daniel Payne on 12-04-2012 at 12:19 pm
Categories: Aldec, EDA, FPGA

I’ve used FPGA vendor-supplied tools from both Xilinxand Lattice Semibefore, so I wanted to see what EDA tools Aldec has to offer for FPGA design. I read the Aldecwhite paper, Corporate Standardization of FPGA Design Flow, and summarize what I found.… Read More

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What I Learned About FPGA-based Prototyping

What I Learned About FPGA-based Prototyping
by Daniel Payne on 11-15-2012 at 8:10 pm
Categories: Aldec, EDA, FPGA

Today I attended an Aldec webinar about ASIC and SoC prototyping using the new HES-7 Board. This prototyping board is based on the latest Virtex-7 FPGA chips from Xilinx.

You can view the recorded webinar here, which takes about 30 minutes (should be available in a few days). I first blogged about the HES-7 two months ago, ASIC Prototyping… Read More

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The logic of trusting FPGAs through DO-254

The logic of trusting FPGAs through DO-254
by Don Dingee on 11-13-2012 at 8:15 pm
Categories: Aldec, EDA, FPGA

Any doubters of the importance of FPGA technology to the defense/aerospace industry should consider this: each Airbus A380 has over 1000 Microsemi FPGAs on board. That is a staggering figure, especially considering the FAA doesn’t trust FPGAs, or the code that goes into them.… Read More

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A Brief History of Aldec

A Brief History of Aldec
by Daniel Payne on 10-20-2012 at 5:31 pm
Categories: Aldec, EDA

Dr. Stanley Hyduke founded Aldecin 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Aldec maintains… Read More

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12m FPGA prototyping sans partitioning

12m FPGA prototyping sans partitioning
by Don Dingee on 10-16-2012 at 9:30 pm
Categories: Aldec, EDA, FPGA

FPGA-based prototyping brings SoC designers the possibility of a high-fidelity model running at near real-world speeds – at least until the RTL design gets too big, when partitioning creeps into the process and starts affecting the hoped-for results.

The average ASIC or ASSP today is on the order of 8 to 10M gates, and that includes… Read More

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EDA Solutions at Ultra Low Power Developer Forum Demonstrates Mixed-Signal Flow including Tools from Tanner EDA, Incentia and Aldec

EDA Solutions at Ultra Low Power Developer Forum Demonstrates Mixed-Signal Flow including Tools from Tanner EDA, Incentia and Aldec
by Daniel Payne on 10-04-2012 at 4:49 pm
Categories: Aldec, EDA, Tanner EDA

EDA Solutions, sole representative in Europe for Tanner EDA and Incentia Design Systems, is exhibiting at the ‘Design & Elektronik’ Developer Forum on Ultra Low Power in Munich, Germany, on October 10, 2012, at the Holiday Inn (Munich – City Centre).

EDA Solutions will be presenting its complete analog, digital and… Read More

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Aldec-Altera DO-254

Aldec-Altera DO-254
by Daniel Nenni on 09-25-2012 at 9:58 pm
Categories: Aldec, EDA, FPGA

As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. Requirements… Read More

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ASIC Prototyping with 4M to 96M Gates

ASIC Prototyping with 4M to 96M Gates
by Daniel Payne on 09-17-2012 at 9:30 am
Categories: Aldec, EDA, FPGA
3 Comments

I’ve used Aldec tools like their Verilog simulator (Riviera PRO) when teaching a class to engineers at Lattice Semi, so to get an update about the company I spoke with Dave Rinehart recently by phone. A big product announcement by Aldec today is for their ASIC prototyping system with a capacity range of 4 Million to 96 Million… Read More

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SystemVerilog from Nevada?

SystemVerilog from Nevada?
by Daniel Payne on 08-16-2012 at 10:58 am
Categories: Aldec, EDA

When I think of EDA companies the first geography that comes to mind is Silicon Valley because of the rich history of semiconductor design and fabrication, being close to your customers always makes sense. In the information era it shouldn’t matter so much where you develop EDA tools, so there has been a gradual shift to a wider… Read More

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AMS Programmable Prototype Platforms

AMS Programmable Prototype Platforms
by ahmed.shahein on 05-21-2012 at 10:25 am
Categories: Aldec, EDA, FPGA

AVNET released their 15[SUP]th[/SUP] Xfest this year, a couple of months ago. It was here in Germany last week. It was a well organized event, rich with invaluable technical information and full of decent smart engineers and managers. If you missed it this year register for the next event as soon as you can.

It was a very successful… Read More