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Acquiring Great Power

Acquiring Great Power
by Paul McLellan on 01-20-2012 at 5:11 pm

“Before we acquire great power we must acquire wisdom to use it well”
Ralph Waldo Emerson

Making good architectural decisions for controlling power consumption and ensuring power integrity requires a good analysis of the current requirements and how they vary. Low power designs, and today there really aren’t… Read More


Chip-Package-System workshops

Chip-Package-System workshops
by Paul McLellan on 01-17-2012 at 4:30 pm

Chips, packages and circuit boards (systems, hence CPS) used to be three separate domains with their own tools that barely interacted at all. If you were lucky, reassigning a pin on a package wouldn’t have to be done manually in all 3 places. But now, from a signal integrity, noise, power point of view these three domains must… Read More


Challenges in 3D-IC and 2½D Design

Challenges in 3D-IC and 2½D Design
by Paul McLellan on 12-09-2011 at 5:18 pm

3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges

The power delivery network is a challenge… Read More


RTL Power Models

RTL Power Models
by Paul McLellan on 11-08-2011 at 8:00 am

One of the challenges of doing a design in the 28nm world is that everything depends on everything else. But some decisions need to be made early with imperfect information. But the better the information we have, the better those early decisions will be. One area of particular importance is selecting a package, designing a power… Read More


Noise Coupling

Noise Coupling
by Paul McLellan on 10-24-2011 at 8:47 am

One of the challenges of designing a modern SoC is that the digital parts of the circuit are really something that in an ideal world you’d keep as far away from the analog as possible. The digital parts of the circuit generate large amounts of noise, especially in the power supply and in the substrate, two areas where it is impossible… Read More


Apache on the Road

Apache on the Road
by Paul McLellan on 10-19-2011 at 2:01 pm

There are lots of places that Apache is going to popping up in the next few weeks.

Firstly, Andrew Yang will deliver the keynote on October 24th at the Electrical Performance of Electronic Packaging and Systems (EPEPS) in San Jose. He will be talking about “Chip-Package-System convergence: bridging multiple disciplings… Read More


2.5D and 3D designs

2.5D and 3D designs
by Paul McLellan on 09-07-2011 at 1:54 pm

Going up! Power and performance issues, along with manufacturing yield issues, limit how much bigger chips can get in two dimensions. That, and the fact that you can’t manufacture two different processes on the same wafer, mean that we are going up into the third dimension.

The simplest way is what is called package-in-package… Read More


Top 5 Reasons for Wasting Power

Top 5 Reasons for Wasting Power
by Paul McLellan on 08-19-2011 at 2:27 pm

Traditionally, David Letterman style, we should really have the top 10 reasons for wasting power in semiconductor design, but here are the five big ones.

Starting with reason #5: Lack of a power gating strategy
Leakage power is a huge proportion of total power and the only way to save leakage power (apart from low leakage cells when… Read More


ANSYS Regional Conference

ANSYS Regional Conference
by Paul McLellan on 08-17-2011 at 3:15 pm

Next Tuesday, August 23rd, is the ANSYS Regional Conference for Silicon Valley. It takes place at the Techmart Network Meeting Center. Apache has three presentations during the day:

  • 9.25-9.45 Andrew Yang Introducing Apache Design Solutions
  • 11.00-11.30 Methodology for delivering power-efficient designs from concept to
Read More

ANSYS/Apache

ANSYS/Apache
by Paul McLellan on 08-13-2011 at 2:43 pm

Last week I met with Andrew Yang, erstwhile CEO of Apache Design Systems and now formally President of Apache Design Inc, a wholly owned subsidiary of ANSYS. The merger formally closed at the start of the month. Within ANSYS Apache is positioned as Chip-aware System-level Engineering Simulation. ANSYS is pretty much completely… Read More