“Before we acquire great power we must acquire wisdom to use it well”
Ralph Waldo Emerson
Making good architectural decisions for controlling power consumption and ensuring power integrity requires a good analysis of the current requirements and how they vary. Low power designs, and today there really aren’t any other types, makes this worse since both clock-gating and power-gating can cause much bigger transitions (especially when re-starting a block) than in designs where the power is delivered in a more continuous way.
The biggest challenge is that good decisions must be made early at the architectural level, but the fully-detailed design data required to do this accurately is obviously not all available until the design has finished. But obviously the design cannot be finished until the power architecture has been finalized. So the key question is whether early power analysis can deliver sufficient accuracy to guide power grid prototyping and chip-package co-design and so break the cycle of this chicken-egg problem.
Early analysis at the RTL level seems to offer the best balance between capacity and accuracy. Higher levels than RTL don’t really offer realistic full-chip power budgeting and levels lower than RTL are too late in the design cycle and also are dependent on the power architecture. But even at the RTL level the analysis must take account of libraries, process, clock-gating, power domains and so on.
Getting a good estimate of overall power is one key parameter, but it is also necessary to discover the design’s worst current demands across all the operating modes. Doing this at the gate-level is ideal from an accuracy point of view but leaves it too late in the design cycle. Again, moving up to RTL is the solution. Clever pruning of the millions of vectors can locate the power-cricitcal subset of cycles consuming worst transient and peak power and dramatic reduce the amount of analysis that needs to be done.
Once all this is identified, it is possible to create an RTL Power Model that can be used for the architectural power decisions. In particular, planning the power delivery network (PDN) and doing true chip-package co-design. Doing this early avoids late iterations and the associated schedule slips, always incredibly costly in a consumer marketplace (where most SoCs are targeted today).
See Preeti Gupta’s full analysis here.Share this post via:
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