SEMICON West – Harry Levinson and Mike Lercel Interview

SEMICON West – Harry Levinson and Mike Lercel Interview
by Scotten Jones on 08-02-2016 at 12:00 pm

On Tuesday morning at SEMICON I had the opportunity to sit down with Harry Levinson, Sr. Director of Technology Research and Sr. Fellow at Global Foundries and Michael Lercel, Director of Strategic Marketing at ASML to discuss the state of lithography.

I opened the discussion with a question about how we are going to address lithography… Read More


SEMICON West – Leti FDSOI and IOT, status and roadmap

SEMICON West – Leti FDSOI and IOT, status and roadmap
by Scotten Jones on 07-28-2016 at 7:00 am

On Tuesday, July 12th at SEMICON West I had an opportunity to sit down with Marie Semeria, the CEO of Leti and discuss the status and future of FDSOI. Leti pioneered FDSOI 15 years ago and has been the leading FDSOI research ever since.

Two years ago Leti and ST Micro demonstrated products on 28nm that are cost competitive with bulk technology.… Read More


IMEC Technology Forum at SEMICON – Coventor could save you billions!

IMEC Technology Forum at SEMICON – Coventor could save you billions!
by Scotten Jones on 07-22-2016 at 7:00 am

The development of leading edge semiconductor technology is incredibly expensive, with estimates ranging from a few to several billion dollars for new nodes. The time to develop a leading edge process is also a critical competitive issue with some of the largest opportunities awarded based on who is first to yield on a new node.… Read More


IMEC-Horizontal Nanowires for 5nm at the VLSI Technology Symposium

IMEC-Horizontal Nanowires for 5nm at the VLSI Technology Symposium
by Scotten Jones on 07-21-2016 at 12:00 pm

At the VLSI Technology Symposium, IMEC presented a paper entitled “Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Silicon Wafers”. I have wanted to blog about this paper since the symposium was held but also wanted to tie it in with an interview… Read More


IMEC Technology Forum (ITF) – Secrets of Semiconductor Scaling

IMEC Technology Forum (ITF) – Secrets of Semiconductor Scaling
by Scotten Jones on 06-07-2016 at 4:00 pm

IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.… Read More


IMEC Technology Forum (ITF) – Moving the Electronics Industry Forward

IMEC Technology Forum (ITF) – Moving the Electronics Industry Forward
by Scotten Jones on 06-02-2016 at 4:00 pm

IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.

Gary Patton is the Chief Technical Officer and Senior… Read More


IMEC Technology Forum (ITF) – EUV When, Not If

IMEC Technology Forum (ITF) – EUV When, Not If
by Scotten Jones on 05-28-2016 at 7:00 am

For me personally EUV has been something of a roller coaster ride over the last several years. I started out a strong believer in EUV but then at the SPIE Advanced Lithography Conference in 2014 TSMC gave a very negative assessment of EUV, and there was a SEMATECH paper on high NA EUV that struck me as extremely unlikely to succeed. I … Read More


IMEC Technology Forum (ITF) – IC Innovation

IMEC Technology Forum (ITF) – IC Innovation
by Scotten Jones on 05-25-2016 at 7:00 am

IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.

Luc Van Den Hove is the president and CEO of IMEC and he… Read More


3D NAND – Moore’s Law in the third dimension

3D NAND – Moore’s Law in the third dimension
by Scotten Jones on 05-07-2016 at 4:00 am

For more than a decade 2D NAND has been the leading driver of lithography shrinks, for example, Samsung went from 120nm in 2003 to 16nm in 2014 with shrinks on an almost yearly basis, but the shrinks came at a price. At 16nm Self Aligned Quadruple Pattering (SAQP) was required for the most critical layers and patterning related costs… Read More