Back in the early 1980’s during the nascent years of electronic design automation (EDA), I worked at Texas Instruments supporting what would become their merchant ASIC business. Back then, life was a bit different. The challenge we faced was to make our ASIC library available on as many EDA flows as we could to give as many users as… Read More
Author: Mitch Heins
Why Open and Supported Interfaces Matter
Webinar Alert: High Bandwidth Memory ASIC SiPs for HPC and Networking Applications
Calling all ASIC designers working on High-Bandwidth Memory (HBM) access architectures in high-performance computing (HPC), networking, deep learning, virtual reality, gaming, cloud computing and data center applications. You won’t want to miss this upcoming webinar focused on system integration aspects of a HBM2 ASIC… Read More
Whitepaper : The True Costs of Process Node Migration
Mentor, A Siemens Business, just released a new white paper entitled, “The True Costs of Process Node Migration” written by John Ferguson. This is a good quick read that highlights some of the key areas that are often over looked when contemplating a shift of process nodes for your next design.
When considering a shift to a more advanced… Read More
ClioSoft’s designHUB Debut Well Received
It was only back in May of this year that ClioSoft first introduced designHUB, a revolutionary new product that is meant to enable better use of intellectual property (IP) within a company. I wrote a SemiWiki article at the time of the announcement and mentioned it again in a lead-up article to the 54[SUP]th[/SUP] Design Automation… Read More
ARM and Cadence IP Simplify IoT System Design and Verification
As the Internet-of-Things (IoT) markets mature, we are seeing the complexity of IoT systems evolve from simple routing functions that connect IoT edge devices to the cloud into more complex system of systems that manage the interaction between multiple sensor-hubs. IoT sensor-hubs and gateways not only take care of basic care… Read More
High Density Advanced Packaging Trends
Thursdays at the Design Automation Conference (DAC) are always a good time to catch up on areas of technology which are adjacent to that which you normally work. The exhibit floor is over and you have more time to spend in seminars. At this year’s DAC, I took advantage of a half day seminar put on by Mentor, a Siemens business, … Read More
NetSpeed’s Pegasus Last-Level Cache IP Improves SoC Performance and Reduces Latency
Memory is always a critical resource for a System-on-Chip (SoC) design. It seems like designers are always wanting more memory, and the memory they have is never fast enough to keep up with the processors, especially when using multi-core processors and GPUs. To complicate matters, today’s SoC architectures tend to share memory… Read More
Cadence’s Tempus – New Hierarchical Approach for Static Timing Analysis
While at the 54[SUP]th[/SUP] Design Automation Conference (DAC) I had the opportunity to talk with Ruben Molina, Product Management Director for Cadence’s Tempus static timing analysis (STA) tool. This was a good review of how the state-of-the-art for STA has evolved over the last couple decades. While the basic problem hasn’t… Read More
Mentor & Phoenix Software Shed Light on Integrated Photonics Design Rule Checking
Just prior to the opening of the 54[SUP]th[/SUP] Design Automation Conference, Mentor, a Siemens company, and PhoeniX Software issued a press release announcing a new integration between their tools to help designers of photonic ICs (PICs) to close the loop for manufacturing sign-off verification. This is a significant piece… Read More
Capture the Light with Integrated Photonics
I wrote up a quick article in the weeks before the Design Automation Conference (DAC) letting readers know that Integrated Photonics were indeed coming to DAC again this year. As a follow up, I attended the DAC presentation, ‘Capture the Light. An Integrated Photonics Design Solution from Cadence, Lumerical and PhoeniX Software’,… Read More
Intel High NA Adoption