R&D Engineer, Staff
Website Synopsys
Academic Qualification
- B.E / B.Tech/ M. Tech. in Electronic & Communication / Computer Science Engineering
Skills Required
- Programming concepts in C/C++ , OOPS
- Should have good understanding of digital design concepts.
- Knowledge of HDL language System Verilog, Verilog required.
- Experience with Perl / TCL / some scripting language is a plus.
- Protocol knowledge of any of ENET, HDMI. MIPI, AMBA, UART etc is added advantage.
- Knowledge of UVM and Functional verification will be a plus.
- Good communication skills and team player.
- Must be flexible, resourceful and responsible to complete assigned tasks within limited resources.
Why NA is Not Relevant to Resolution in EUV Lithography