Design Engineer II
Website Cadence
Responsibilities:
- Custom layout design for PHY IP development – Understand design requirements and work closely with the design team and successfully deliver Analog layouts.
- Perform physical verifications like DRC/LVS/Reliability and fixing violations
Requirements
- Hands on layout experience in various analog IP like Opamps, Bandgaps, Dataconverters, LDO and PLL etc.
- Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
- Knowledge of various analog layout techniques like matching, shielding etc.,
- Good understanding of DSM technology methodology, issues etc.,
- Having worked on latest technology nodes, 28nm and below, is desired.
- Must have good communication skills and should be team player.
- Scripting and automation experience is a plus.
Intel High NA Adoption