Sr. Staff Engineer for PCIe Subsystem Verification
Website Achronix
The India Technology Center leads all SoC development at Achronix Semiconductor, working on end-to-end design development, from architecture development all the way to chip tape-out for Achronix’s Speedster and Speedcore class of FPGAs. The team owns the design of various high-speed SerDes, memory and NoC architecture subsystems, maximizing the data bandwidth and latency in and out of Achronix FPGAs.
Job Description/Responsibilities
The opening is for a verification lead who is responsible for the verification of different SerDes subsystems that go into Achronix’s Speedster class of FPGAs, specifically PCIe Gen3/4/5 and related CXL/CCIX and other standards. This employee will be responsible for module- and integration-level RTL verification, as well as performance modeling. This employee is expected to take independent ownership of complex design challenges. The primary responsibilities include:
- Lead verification planning
- Functional verification at module, subsystem, full-chip levels
- Testbench design
- Lead ATE functional vector generation
- Post-Si support
- Mentor other engineers
- Review other designs’ verification goodness
- Drive verification methodologies and best practices
This employee is also expected to participate regularly in interactions with global teams spanning systems, software and product engineering.
Required Skills
- Expertise with SerDes-related protocols and verification, specifically PCIe Gen3/4/5
- Expertise in CCIX or CXL is a plus
- Expertise in verification methodologies, especially UVM or CRV
- Strong automation and scripting experience, especially in Python and/or Perl
- Experience with post-Si bring-up and debug
- Strong verbal and written communication skills
- Ability to work in a dynamic and fast-paced environment, with a proactive mindset
- Prior experience with providing technical mentoring to junior engineers
- Experience with formal verification tools is a plus
Education and Experience
- Preferred BS/MS + 9+ years of experience in RTL design and verification
- At least four years of experience in SerDes protocols’ design verification
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