SiC 800 2026ChipletSummit Static (1)

SiFive’s AI’s Next Chapter: RISC-V and Custom Silicon

SiFive’s AI’s Next Chapter: RISC-V and Custom Silicon
by Daniel Nenni on 02-18-2026 at 2:00 pm

AI’s Next Chapter RISC V and Custom Silicon

In the rapidly evolving world of artificial intelligence and semiconductor design, open-standard processor architectures are gaining unprecedented traction. At the center of this shift is SiFive, a company founded by the original creators of the RISC-V ISA, which champions an open, extensible, and license-free alternative… Read More


Smarter IC Layout Parasitic Analysis

Smarter IC Layout Parasitic Analysis
by Daniel Payne on 02-18-2026 at 10:00 am

ParagonX flow

IC layout parasitics dominate the performance of custom digital, analog and mixed-signal designs, so the challenge becomes how to identify the root causes and to quantify the effects of parasitics during early design stages. The old method of iterating between layout, extraction, SPICE simulation, followed by manual debug… Read More


Improving Retrieval Accuracy in AI

Improving Retrieval Accuracy in AI
by Bernard Murphy on 02-18-2026 at 6:00 am

Agentic RAG expert

While there are big ambitions for virtual engineers and other self-guiding agentic applications, today estimates show 83-90% of AI inferences are for internet searches. On a related note, chatbots are now said to account for nearly 60% of internet traffic. Search and support are the biggest market drivers for automation and … Read More


Ceva IP: Powering the Era of Physical AI

Ceva IP: Powering the Era of Physical AI
by Daniel Nenni on 02-17-2026 at 2:00 pm

Ceva IP Powering the Era of Physical AI

Artificial intelligence is rapidly moving beyond the digital domain and into the physical world. From autonomous robots and smart factories to intelligent vehicles and connected consumer devices, AI systems are increasingly expected to perceive their surroundings, make real-time decisions, and act on them instantly. This… Read More


Accelerating Static ESD Simulation for Full-Chip and Multi-Die Designs with Synopsys PathFinder-SC

Accelerating Static ESD Simulation for Full-Chip and Multi-Die Designs with Synopsys PathFinder-SC
by Kalar Rajendiran on 02-17-2026 at 10:00 am

SNPS PathFinder SC ESD Verification

As analog and mixed-signal designs become increasingly complex, parasitic effects dominate both design time and cost, consuming 30–50% of engineers’ effort in debugging and reanalyzing circuits. Addressing these multiphysics effects requires early verification strategies and reliable simulation solutions. Modern … Read More


A Century of Miracles: From the FET’s Inception to the Horizons Ahead

A Century of Miracles: From the FET’s Inception to the Horizons Ahead
by Daniel Nenni on 02-17-2026 at 6:00 am

From the FET’s Inception to the Horizons Ahead

The Field-Effect Transistor (FET), a cornerstone of modern electronics, marks its centennial in 2025, tracing back to Julius Edgar Lilienfeld’s groundbreaking invention in 1925. Born in 1882 in what is now Lviv, Ukraine, Lilienfeld was a prolific physicist who earned his PhD from Berlin University in 1905. His early … Read More


Two Open RISC-V Projects Chart Divergent Paths to High Performance

Two Open RISC-V Projects Chart Divergent Paths to High Performance
by Jonah McLeod on 02-16-2026 at 2:00 pm

yun chip hier

Up to now the RISC-V community has been developing open-source processor implementations to a stage where they can appeal to system designers looking for alternatives to proprietary Arm and x86 cores. Toward this end, two projects have emerged as particularly significant examples of where RISC-V is heading. One is Ara, a vector… Read More


On the high-speed digital design frontier with Keysight’s Hee-Soo Lee

On the high-speed digital design frontier with Keysight’s Hee-Soo Lee
by Don Dingee on 02-16-2026 at 10:00 am

Chiplet 3D Interconnect Designer reduces interconnect analysis in high-speed digital design from weeks to minutes

High-speed digital (HSD) design is one of the more exciting areas in EDA right now, with design practices, tools, and workflows evolving to keep pace with increasing design complexity. With the annual Chiplet Summit and DesignCon festivities right around the corner, we sat down with Keysight’s Hee-Soo Lee, HSD Segment Lead, … Read More


Samtec Ushers in a New Era of High-Speed Connectivity at DesignCon 2026

Samtec Ushers in a New Era of High-Speed Connectivity at DesignCon 2026
by Mike Gianfagna on 02-16-2026 at 10:00 am

Samtec Ushers in a New Era of High Speed Connectivity at DesignCon 2026

As I’ve discussed before, Samtec has a way of dominating every trade show the company participates in. The upcoming DesignCon event is no exception. At the show, Samtec will be discussing data rates up to 448 Gbps and signals up to 130 GHz. Beyond a rich set of demonstrations in the company’s booth, Samtec engineers will be participating… Read More


Bronco Debug Stress Tested Measures Up

Bronco Debug Stress Tested Measures Up
by Bernard Murphy on 02-16-2026 at 6:00 am

Automated debugger

I wrote last year about a company called Bronco, offering an agentic approach to one of the hottest areas in verification – root-cause debug. I find Bronco especially interesting because their approach to agentic is different than most. Still based on LLMs of course but emphasizing playbooks of DV wisdom for knowledge capture … Read More