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Podcast EP303: How Lattice Semiconductor is Addressing Security Threats From the Ground Up with Mamta Gupta

Podcast EP303: How Lattice Semiconductor is Addressing Security Threats From the Ground Up with Mamta Gupta
by Daniel Nenni on 08-15-2025 at 6:00 am

Dan is joined by Mamta Gupta, She leads the Security Product Marketing, Datacenter and the Communications Segment Marketing Teams at Lattice. She brings with her over 20 years of FPGA experience in product development with special focus on security, aerospace and defense segments.

Dan explores the growing area of cybersecurity… Read More


Semiconductors Still Strong in 2025

Semiconductors Still Strong in 2025
by Bill Jewell on 08-14-2025 at 2:00 pm

Semiconductor Market Change 2025

The global semiconductor market in 2Q 2025 was $180 billion, up 7.8% from 1Q 2025 and up 19.6% from 2Q 2024, according to WSTS. 2Q 2025 marked the sixth consecutive quarter with year-to-year growth of over 18%.

The table below shows the top twenty semiconductor companies by revenue. The list includes companies which sell devices… Read More


Moving Beyond RTL at #62DAC

Moving Beyond RTL at #62DAC
by Daniel Payne on 08-14-2025 at 10:00 am

beyond rtl min

Hardware designers have been using RTL and hardware description languages since the 1980s, yet many attempts at moving beyond RTL have tried to gain a foothold. At the #62DAC event I spent some time with Mike Fingeroff, the Chief High-Level Synthesis Technologist to understand what his company Rise Design Automation is up to. … Read More


Streamlining Functional Verification for Multi-Die and Chiplet Designs

Streamlining Functional Verification for Multi-Die and Chiplet Designs
by Daniel Nenni on 08-14-2025 at 6:00 am

Streamlining Functional Verification for Multi Die and Chiplet Designs

As multi-die and chiplet-based system designs become more prevalent in advanced electronics, much of the focus has been on physical design challenges. However, verification—particularly functional correctness and interoperability of inter-die connections—is just as critical. Interfaces such as UCIe or custom interconnects… Read More


S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China

S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China
by Daniel Nenni on 08-13-2025 at 10:00 am

pic 1 (1)

Shanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at RISC-V Summit China 2025, highlighting its contributions to the ecosystem. The company also played a leading role in the EDA sub-forum, with VP Ying… Read More


A Quick Tour Through Prompt Engineering as it Might Apply to Debug

A Quick Tour Through Prompt Engineering as it Might Apply to Debug
by Bernard Murphy on 08-13-2025 at 6:00 am

Prompt ENgineering example

The immediate appeal of large language models (LLMs) is that you can ask any question using natural language in the same way you would ask an expert, and it will provide an answer. Unfortunately, that answer may be useful only in simple cases. When posing a question we often implicitly assume significant context and skate over ambiguities.… Read More


Chiplets and Cadence at #62DAC

Chiplets and Cadence at #62DAC
by Daniel Payne on 08-12-2025 at 10:00 am

SoC Cockpit Concept min

Using chiplets is an emerging trend well-covered at #62DAC and they even had a dedicated Chiplet Pavilion, so I checked out the presentation from Dan Slocombe, Design Engineering Architect in the Compute Solutions Group at Cadence. In a short 20 minutes Dan managed to cover a lot of ground, so this blog will summarize the key  points.… Read More


What XiangShan Got Right—And What It Didn’t Dare Try

What XiangShan Got Right—And What It Didn’t Dare Try
by Jonah McLeod on 08-12-2025 at 6:00 am

XiangShan

An Open ISA, a Closed Mindset — Predictive Execution Charts a New Path

The RISC-V revolution was never just about open instruction sets. It was a rare opportunity to break free from the legacy assumptions embedded in every generation of CPU design. For decades, architectural decisions have been constrained by proprietary patents,… Read More


The Critical Role of Pre-Silicon Security Verification with Secure-IC’s Laboryzr™ Platform

The Critical Role of Pre-Silicon Security Verification with Secure-IC’s Laboryzr™ Platform
by Kalar Rajendiran on 08-11-2025 at 10:00 am

Pre Silicon Security Verification (Hardware SCA)

As embedded systems and System-on-Chip (SoC) designs grow in complexity and integration, the risk of physical attacks has dramatically increased. Modern day adversaries no longer rely solely on software vulnerabilities; instead, they exploit the physical properties of silicon to gain access to sensitive data. Side-channel… Read More


Should Intel be Split in Half?

Should Intel be Split in Half?
by Daniel Nenni on 08-11-2025 at 6:00 am

Intel Should Not Be Split!

A recent commentary from four former Intel board members argue that Intel should be split into two separate companies with separate CEOs and separate board of directors. Charlene BarshefskyReed HundtJames Plummer, and David Yoffie wrote that Intel shareholders should insist on a split which would create a new, independent,… Read More