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Tanner EDA
Posted on by Daniel Payne

A New Digital Place and Route System

A New Digital Place and Route System
by Daniel Payne on 04-07-2014 at 10:00 am
Categories: EDA, Tanner EDA

IC place and route tools can be very high-priced EDA software to purchase or lease, so there’s some good news for AMS designers that need an affordable digital place and route tool for their mostly analog designs. Today the team at Tanner EDAannounced a totally new place and route system has been added to their Schematic Driven Layout (SDL)tool. I spoke with their CTO, Massimo Sivilotti on Friday to ask some questions.



Q & A

Q: What’s different with this P&R system? I recall that you’ve offered place and route tools before.

It’s an all new system for us, there is no code re-use with our previous P&R tools. It is standards-driven and accepts LEF, DEF and standard PDK formats. Our old router was a channel router, and the placer worked with two or three levels of interconnect. Our new router is not limited in the number of layers of interconnect and achieves 100% utilization of routing.

Q: Why introduce a new P&R tool?

In the bigger picture we’ve just completed a complete AMS IC design flow with:

  • Mixed-signal simulation
  • Logic synthesis
  • And now Place and Route

Q: Where did this new P&R technology all come from?

We did it ourselves, and it all started from a professor and his PhD student at the State University of NY. We’ve hired the PhD as an employee and integrated this new technology into our IC AMS tool flow.

Q: What is the typical capacity of a P&R job for your AMS customers?

About 50K instances or less is typical usage for AMS designers with mostly analog design plus digital content. 16GB of RAM is sufficient to run designs of this size. Run times are typically in the hours range and the tool is run in a batch mode.

Q: Which foundries have you verified this new router on so far?

The two most notable fabs are X-Fab and TowerJazz, so our customers have taped-out their AMS designs there with the new P&R system. Most of our customers are doing AMS design at the 65nm node and previous generations.

Q: When is this new tool available?

We’ve had our early customers using this new system over the past 12 months, and now we’re ready for general distribution in release v16.1 of HiPer Silicon Design Suite.

Q: If I own the old P&R tool, how do I get this new one?

This is a totally new product, so give us a call to learn about how to upgrade.

Q: How difficult is this P&R to learn?

At first we recommend that you try the tutorial example. The tool can be used for chip assembly, intra-block routing, even analog routing. You should be up and running in a day or two, and you can also talk with an AE or do a web-ex to get support.

Q: What platforms does this software run on?

It runs on Windows 8.1, Windows 8 and Windows 7 now. Next month it will be available also on Linux.

Further Reading

lang: en_US

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