FD-SOI is Worth More Than Two Cores

This is the second blog entry about an ST Ericsson white-paper on multiprocessors in mobile. The first part was here.

The first part of the white-paper basically shows that for mobile the optimal number of cores is two. It is much better to use process technology (and good EDA) to run the processor at higher frequency rather than add additional cores.

ST Ericsson, as belies its name, is partially owned by ST (although they are trying to get rid of it, as are Ericsson. Dan Nenni has the same problem with his kids, they just hang around and cost a lot of money). Unlike everyone else who has decided the future is FinFET, ST has decided to go with FD-SOI (Chenming Hu was better at naming transistors than whoever came up with that mouthful). FD stands for fully-depleted, meaning that the channel area under the gate is not doped at all. SOI stands for silicon-on-insulator since the base wafer is an insulator. One of the advantages that FD-SOI has over FinFET is that it is essentially a planar process very similar to all existing processes and so can be build using very mature technology with fewer process steps than “other” processes (by which I read FinFET).

Compared to a bulk transistor, the advantages of FD-SOI are that it is faster and lower power. In a given technology node the channel is shorter and it is fully-depleted, both result in up to 35% higher operating frequency for the same power at high voltage and up to 100% faster at low voltage. The fully depleted channel removes drain-induced parasitic effects and has better confinement of carriers from source to drain, a thicker gate dielectric reducing leakage and so on. The result is power reductions of 35% at high performance and 50% at low operating points.

So for a processor, obviously, it can be run at a higher frequency for the same voltage/power or run at the same frequency without consuming so much power. The maximum achievable frequency is higher. And the process can operate at lower voltages with reasonably high frequencies (such as 1GHz at 0.65V).

This 35% increase in efficiency a high frequencies is more than enough for FD-SOI dual processors to outperform slower bulk quad-processors due to the limited software scalability. It also can obviate the need to optimize power by using heterogeneous big.LITTLE type architectures which requires complex hardware and sophisticated control mechanisms that are not yet mature.

ST Ericsson was an early adopter of dual processors but have resisted moving to quad core for all the reasons in these papers. However, this is probably academic. ST Ericsson has struggled to find major customers (partially because Apple and Samsung take most of the market and roll their own chips, and their biggest customer was Nokia who switched to Microsoft WP which only runs on Qualcomm chips). ST and Ericsson both have announced that they want to “explore strategic options” for STE (aka find a buyer) but it may end up that the company ends up simply being shut down. The group that I worked with at VSLI Technology in the 1990s, ended up inside NXP and was then folded into ST Ericsson. I notice on their blog entries the names of some people that used to work for me.

Download the white-paper here.