Sonics opens new strategy for SoC energy processing

Back in February when we shared the Sonics philosophy on the ICE-Grain Power Architecture for hardware-based SoC power management, I speculated we’d know more by DAC 2016. Sonics is hitting the road with a new live seminar coming to Silicon Valley this month and Austin during DAC – and the news is big.

On second thought, maybe it’s small. Computer architecture tends to move in cycles. To design the future, it helps to understand the past, because the problems being solved are fundamentally similar. When Sonics CTO Drew Wingard described his latest idea to me, I thought it sounded a bit familiar conceptually, shrunk down to meet our IP-driven times.

Once upon a time when data centers began to look like blade farms, people were searching for ways to remotely manage hundreds or thousands of systems, many with varying methods. Intel led an initiative to create the Intelligent Platform Management Interface (IPMI) that standardized protocols and defined a microcontroller block (the baseboard management controller, or BMC) running independently of the operating system. BMCs provide monitoring of system features, alerts, and in dire cases a system-level reset, out-of-band to the CPU.

IPMI is really more monitoring than management. For active power management needs, MIPI defined the System Power Management Interface (SPMI). It connects an SoC to other SoCs and peripheral chips on a two-wire bus with a very simple protocol. This was necessary to manage features not integrated in the mobile SoC itself, such as external basebands and cameras.

These and other always-on PC methods like Intel Ready Mode Technology are still coarse-grained. Managing power with the system CPU running software is possible, but there are penalties to that. As we described back in February, fine-grained power management of a highly integrated mobile or IoT SoC with hardware techniques is becoming a must have.

Dynamically managing power is not for the faint of heart. I was at a recent conference where a product manager at Synopsys described the sad story of a printer vendor who had managed to get enough SoC blocks powered down to meet the power consumption target, but then could not get the SoC powered back up because an IP block they needed was off.

It’s the classic power management deadlock. Figuring out all the dependencies while stuff catches up often leaves CPU software too late to push the right button. What Sonics is preparing to talk about is a reprogrammable hardware power management architecture – an Energy Processing Unit.

The starting point is the CPU manages the active moments in the SoC, while the EPU manages the idle moments in the SoC. The EPU handles all the different varieties of power management techniques with order-of-magnitude faster control compared to software, providing a verifiable solution that is better by construction (not by chance of twiddling the right bits in the right order and timing in software).

The fine-grained approach to SoC power has a larger number of smaller pieces and a larger opportunity for idling to reduce power, if one can handle the sequences correctly. Take the power management diagram we shared previously – this is just one sequence. In the real world, there may be several sequences underway simultaneously, with varying complexity and timing.

Now, Wingard and his team are ready to tell the full EPU story with use models and example data. They shared one preview from the seminar, this ICE-G1 EPU cluster view.

This screen from SonicsStudio shows the four power states of the cluster in the center diagram. In the window on the right are the table views of the power states, the transitions between the states, and other state attributes. In the two windows on the left are the hierarchical project and cluster outline views with optional RTL outline view. The bottom window tabs display details: the configuration design properties; the problems as the design is captured; a Tcl console that enables execution of commands in script form; and the design compilation output.

Sonics has already introduced the ICE-G1 EPU IP product:
Sonics Develops Industry’s First Energy Processing Unit Based on the ICE-Grain Power Architecture

Registration for both the Silicon Valley (May 25[SUP]th[/SUP]) and Austin (June 6[SUP]th[/SUP]) live seminars is here, seating is limited and we expect seats to go quickly:
Introducing ICE-G1™, the industry’s first complete EPU

I like the EPU moniker – it will be fascinating to see how this is adopted and which other vendors follow.