Dolphin will hold a live webinar on November 15, 9:00 AM PST or November 22, 10:00 AM GMT. This webinar targets the SoC designers wanting to learn how to quickly implement ultra-low power (uLP) techniques, using proven recipes.… Read More
Back in February when we shared the Sonics philosophy on the ICE-Grain Power Architecture for hardware-based SoC power management, I speculated we’d know more by DAC 2016. Sonics is hitting the road with a new live seminar coming to Silicon Valley this month and Austin during DAC – and the news is big.… Read More
By offering low-power PCI Express PHY solution for mobile application! To make it clear, we are not talking about Mobile Express (M-PCIe), but clearly about PCI Express protocol, including a PCIe Controller and a PCIe PHY. Initially developed to support internal connection between the CPU and the GPU in a PC, the technology has… Read More
There was recently a forum discussion about the best low power techniques. Not surprisingly we didn’t come up with a new technique nobody had ever thought of but it was an interesting discussion.
First there are the techniques that by now have become standard. If anyone wants more details on these then two good resources are… Read More
Traditionally, David Letterman style, we should really have the top 10 reasons for wasting power in semiconductor design, but here are the five big ones.
Starting with reason #5: Lack of a power gating strategy
Leakage power is a huge proportion of total power and the only way to save leakage power (apart from low leakage cells when… Read More
