Architecture Exploration of Processors and SoC to trade off power and performance 5
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3D TCAD Simulation for Power Devices

3D TCAD Simulation for Power Devices
by Daniel Payne on 08-30-2019 at 10:00 am

My first IC design back in 1978 was a DRAM and it ran on 12V, 5V and -5V, but then my second DRAM was using only a 5V supply. Today we see SOCs running under a 1V supply voltage, but there is a totally different market for power devices that are at the other end of the voltage spectrum and they handle switching ranges from 12V – 250V. To learn more about power devices and how the process and device modeling is done, I read a Silvaco publication entitled Advanced Process and Device 3D TCAD Simulation of Split-Gate Trench UMOSFET.

For vertical discrete power MOSFETs there are two important specifications that engineers look at:

  • Breakdown voltage (BV)
  • Specific on-state resistance (RSP)

A couple of approaches have been used for power devices: Trench MOSFETs, RSO MOSFETs. The winning approach has been the Split-Gate RSO MOSFETs because of their low channel resistance, plus ultra-low drift region resistance with a smaller Cgd (gate-to-drain capacitance), improving switching speeds.

Process engineers use 3D TCAD tools to model power devices and optimize them by looking at the predicted values of:

  • Capacitance-Voltage (C-V)
  • Current-Voltage (I-V)
  • Breakdown Voltage (BV)

Silvaco provides Victory Process and Victory Device simulators to do this modeling of power devices. So let’s start with a 3D process simulation of a Split-Gate UMOSFET, where Victory Process is used to build the device structure. Several simulated process steps  are shown below:

a) Formation of a deep trench with rounded bottom, both dry and wet etch steps

b) Shield oxide growth

c) Shield poly deposition

d) Inter-poly oxide deposition and etch back

e) Gate poly deposition and etch back

f) Core contact etching and deposition of the contact plug

Silvaco: Split Gate, Figure 1
Victory Process simulation of key process steps to fabricate the Split-Gate UMOSFET

A 3D numerical mesh is the next step using the Victory Mesh tool, and a 3D Delaunay mesh was generated to accurately resolve the 3D geometrical features. Here’s the result of meshing:

Silvaco: Meshing
Delaunay mesh to resolve complex 3D geometry features (a) and doping profiles (b)

3D device simulations are then run with the Victory Device simulator, and this is quite powerful because it can model 3D unstructured tetrahedral meshes for any device shape. To run Victor Device simulations you have several actions:

  • Specify the materials, models and simulation values
  • Simulate steady-state  Id-Vg, gm-Vg, Id-Vd and BV
  • Small-signal (AC) capacitance-voltage (C-V) plot
  • Device switching plots

An initial solution is computed, then Id-Vg curves are produced for each Vds voltage, then transconductance gm-Vg are computed as shown below:

Silvaco: Id-Vg
Computed Id-Vg curve (at Vd=0.1V) and extracted transconductance gm-Vg characteristics

Here’s the plot of Id-Vd at a select Vgs bias voltage:

Silvaco: Id-Vd
Computed Id-Vd output characteristics, for selected Vg bias (Vg = 5V)

A plot of Breakdown I-V is shown where the gate bias Vg = 0V:

Silvaco: Breakdown I-V
Computed Breakdown I-V characteristics, for Vg=0V

Each of these I-V curves was generated by the TonyPlot tool.

C-V plots are simulated with Victory Device, and here’s the small-signal (AC) results showing intrinsic capacitances:

Silvaco: C vs Vg
Computed device Capacitances versus Gate Voltage (Vg)


Process engineers equipped with the proper modeling and simulation tools can now predict the behavior of power devices like Split-Gate Resurf Stepped Oxide (SG-RSO) MOSFET. Instead of running lots of silicon, measuring, tweaking and repeating, engineers can accurately model and optimize virtually, saving lots of time and money. Read the complete article online.

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