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Keeping Moore’s Law Alive

Keeping Moore’s Law Alive
by Paul McLellan on 04-27-2012 at 12:37 pm

At the GSA silicon summit yesterday the first keynote was by Subramanian Iyer of IBM on Keeping Moore’s Law Alive. He started off by asking the question “Is Moore’s Law in trouble?” and answered with an equivocal “maybe.”

 Like some of the other speakers during the day, he pointed out that 28nm will be a long-lived process, since the move to 20nm is not really that compelling (for instance, despite Intel’s $12B investment, comparing Sandy Bridge and Ivy Bridge there is a 4% reduction in power for roughly the same performance).

As most of us know, we lack a viable lithography that is truly cost-effective for 20nm and below. We have a workable technology in double patterning, but the cost of a mask set, the cost of the extra manufacturing steps and the impact on cycle time are enough to knock us off the true Moore’s law trajectory which is not a technology law but an economic one. Namely, that at each process generation the transistors are about half the cost compared to the previous generation. People have successfully created 3nm FinFET transistors using e-beam but that isn’t close to scaling to volume manufacturing.

As Roawen Chen pointed out at the start of the later panel session, sub 20nm we are looking at some steep hills:

  • $200M per thousand wafer starts per month capacity
  • $10B for a realistic capacity fab
  • EUV or double/triple patterning
  • $7M for a mask set
  • $100M per SoC design costs
  • Fab cycle time (tapeout to first silicon) of 6 months (one year with a single respin)

 Subu focused on what he called “orthogonal scaling” meaning scaling other than what we normally call scaling, namely lithographic scaling. And, as he pointed out, IBM is an IDM and so not everything he says is necessarily good for the foundry model.

The first aspect of orthogonal scaling that IBM is using is embedded DRAM. Everyone “knows” that SRAM is much faster than DRAM and this is true. But as memories get larger, the flight time of the address and data is the dominant delay and DRAM starts to perform better since it is smaller (so shorter flights). Plus, obviously, the overall chip is smaller (or you can put more memory).

A second benefit of embedded DRAM is that you can build deep trench capacitors which are 25X more effective per unit area than other capacitors and so can be used heavily for power supply decoupling. This alone gives a 5-10% performance increase, which is an appreciable fraction of a process generation.

Power is the big constraint. But 70-80% of power in a big system is communicating between chips. The processor dissipates about 30% of the power, I/O dissipates about 20% and memory about 30%, but half of the memory power is really I/O. 3D chips give a huge advantage. The distances in the Z direction are much smaller than in the XY direction and you can have much higher bandwidth since you can have thousands of connections and the power dissipation is a lot less than multiplexing a few pins at very high clock rates.

So the reality of Moore’s Law. We have marginally economic lithography at 20nm, unclear after that. EUV is still completely unproven and might not work. Double and triple patterning are expensive (and create their own set of issues since the multiple patterns are not self-aligning leading to greater variation in side-wall capacitance, for example). Ebeam write speed is orders of magnitude too slow. But orthogonal approaches can, perhaps, substitute in at least some cases.


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