The first GSA Silicon Summit will address the complexity, availability and time-to-market challenges that the industry must overcome to enable low power, cost effective solutions to keep pace with Moore’s Law. With never ending customer demand of better, faster and cheaper, semiconductor manufacturers must continually push their technology processes to ensure that they are providing higher density, lower power, and faster processing speeds. This event will evaluate the predominant process technologies that are leading the industry to meet this demand.

APRIL 26th, 2012

Computer History Museum
1401 Shoreline Blvd.
Mountain View, CA 94043

REGISTER NOW!

Program

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| align=”center” valign=”top” | 8:00 a.m.
| valign=”top” | Registration/Networking Breakfast
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| align=”center” valign=”top” | 9:00 a.m.
| valign=”top” | Opening Remarks
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| align=”center” valign=”top” | 9:00 a.m.
| valign=”top” | Keynote Address: Keeping Moore’s Law AliveDr. Subramanian S. Iyer, IBM Fellow and Chief Technologist, Microelectronics Division, IBM
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| align=”center” valign=”top” | 9:30 a.m.
| valign=”top” | Keynote Address: Advancements in CMOS Technologies
Subramani Kengeri, Head of Advanced Technology Architecture, Office of the CTO, GLOBALFOUNDRIES
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| align=”center” valign=”top” | 10:00 a.m.
| valign=”top” | Panel Discussion: Extending the Life of CMOS Moderator:Dr. Roawen Chen, Vice President, Manufacturing Operation, Marvell Semiconductor, Inc.
Panelists:
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• Jim Aralis, Chief Technology Officer and Vice President, R&D, Microsemi

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• Paul Boudre, Chief Operating Officer, Soitec

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• Shung Chieh, Vice President, Technology Development, Aptina Imaging

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• Matt Crowley, Vice President, Hardware Development, Tabula

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• Pushkar Ranade, Senior Director, Process Integration, SuVolta

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| align=”center” valign=”top” | 11:00 a.m.
| colspan=”2″ valign=”top” | [TABLE] style=”width: 100%”
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| Networking Break
Sponsored by True Circuits
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| align=”center” valign=”top” | 11:15 a.m.
| valign=”top” | Keynote Address: The Case for SOI TechnologyJean-Marc Chery, Executive Vice President and Chief Manufacturing & Technology Officer, STMicroelectronics
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| align=”center” valign=”top” | 11:45 a.m.
| valign=”top” | Keynote Address: The Revolutionary Scope of Multi-Gate Transistors Dr. Chenming Hu, TSMC Distinguished Chair Professor of Microelectronics, University of California, Berkeley
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| align=”center” valign=”top” | 12:15 a.m.
| valign=”top” | Lunch
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| align=”center” valign=”top” | 12:45 p.m.
| valign=”top” | Keynote Address: The Multidimensional Landscape Nick Yu, Vice President, Engineering, Qualcomm
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| align=”center” valign=”top” | 1:15 p.m.
| valign=”top” | Panel Discussion: 3D ICEcosystem Collaboration

Moderator:Mark Brillhart, Vice President, Technology and Quality, Cisco Systems, Inc. Panelists:
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• Raman Achutharaman, Corporate Vice President, Strategy & Marketing, Silicon Systems Group, Applied Materials

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• Liam Madden, Corporate Vice President, FPGA Development and Silicon Technology, Xilinx

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• David McCann, Senior Director, Packaging R&D, GLOBALFOUNDRIES

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• Stephen Pateras, Senior Director, Marketing, Silicon Test Division, Mentor Graphics

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• Rich Rice, Senior Vice President, Sales & Engineering, ASE

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| align=”center” valign=”top” | 2:15 p.m.

| valign=”top” | 3D IC Working Group Meeting

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Keynote Address: Keeping Moore’s Law Alive
To sustain Moore’s Law, the industry’s brightest minds have explored the boundaries of technology and innovation to boost computing power at the 22nm and beyond. The stand-out solutions include 2.5D/3D ICs, SOI technology and 3D transistors. This keynote will address how these multiple technologies will further business’ growth and competitive edge in the near future.

Keynote Address:Advancements in CMOS Technologies
Contrary to the belief of some industry pundits that are driven by today’s digital age, the advancement of CMOS technology continues to enable the creation of leading-edge electronics by sustained scalability, accelerated time-to-market and higher yield. This keynote will showcase the resilient lifespan that CMOS performance exhibits today through technical improvements, surpassing its physical and economical limits.

Panel Discussion: Extending the Life of CMOS
Employing CMOS for the next generation of high-performance applications can be challenging, but companies continue to incorporate new process technologies that allow them to continue to maximize the use of CMOS to solve power and scaling issues. This panel session will debate the strengths and weaknesses of the solutions that advance this technology through analyzing the cost trade-offs of their technical merits and other factors, ultimately providing a snapshot of the technologies’ market impact.

Keynote Address: The Multidimensional Landscape
The buzz surrounding 2.5D/ TSV-based 3D technology is gaining momentum in the mainstream market, as more and more companies explore its cost and performance benefits and commit to tackling its technical and non-technical barriers. This keynote will address the breakthrough advances in multidimensional technology and forecast its long-term roadmap.

Keynote Address: The Case for SOI Technology
With significant technical gains in power and performance, SOI is a time-tested technology poised to enable the next generation of processors. This keynote will discuss how SOI technology will enable technological innovation and that will influence the ecosystem in new mobile, data, and consumer applications.

Keynote Address: The Revolutionary Scope of Multi-Gate Transistors
Gordon Moore calls the FinFET/Trigate transistor the most radical shift in semiconductor technology in over forty years. What are the advantages of the multigate FinFET? What makes it scalable to 10nm and single digit nm? What new opportunities are presented by it and its cousin, the ultra-thin-body UTBSOI transistor? This keynote will address the game-changing impact the introduction of multi-gate transistors will have on today’s products.

Panel Discussion: 3D IC Ecosystem Collaboration
The anticipated arrival of 3D ICs is on track for 2013, and as with any unproven technology, the cost, yield and logistical uncertainties are high if a coherent supply chain is not implemented quickly. While the technology continues to progress, the industry is working toward aligning the business goals of chip companies, foundries, packaging/assembly houses and so on. This panel session will discuss what must be accomplished within the supply chain before the debut of 3D ICs, from a standards and technical standpoint.

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