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Deep learning fueling the AI revolution with Interlaken IP Subsystem

Deep learning fueling the AI revolution with Interlaken IP Subsystem
by Daniel Nenni on 07-30-2018 at 7:00 am
Categories: AI, IP, Open-Silicon, Semiconductor Services

AI is revolutionizing and transforming virtually every industry in the digital world. Advances in computing power and deep learning have enabled AI to reach a tipping point toward major disruption and rapid advancement. However, these applications require much higher performance and bandwidth requiring new kinds of IP and that brings us to Open-Silicon and the Interlaken IP.

Open-Silicon, a founding member of the Interlaken Alliance formed in 2007, launched the 8[SUP]th[/SUP]generation of Interlaken IP core supporting up to 1.2 Tbps bandwidth last year. This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable.

The Interlaken IP subsystem originally developed for networking applications is enabling high speed chip to chip interface for deep learning SoCs. Open-Silicon’s eighth-generation Interlaken IP supports up to 1.2Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC). Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. Open-Silicon’s ILKN FEC IP core meet the requirements Interlaken protocol to significantly improve bandwidth by enabling high speed SerDes integration. The FEC can easily achieve a BER (Bit Error Rate) of 10-15, which is required by most electrical interface standards using high speed SerDes built upon a flexible and robust architecture.

The updated Interlaken specification is capable of supporting SerDes beyond 30Gbps and up to 58Gbps—this was mainly because of the introduction of the peer-to-peer service, which allows sending more data on fewer lines. This led to development of Open-Silicon’s eighth generation Interlaken IP core, supporting up to 1.2 Tbps high performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC) https://www.open-silicon.com/open-silicon-ips/interlaken-controller-ip/

Key Features:

  • Fully-programmable SerDes lane mapping
  • Interlaken-LA 4-channel protocol
  • Up to 56 Gbps SerDes support
  • 1.2 Tbps high-bandwidth performance
  • Interlaken Retransmit Extension support

Standard Features:
In addition to the key features highlighted with the latest release, the Open-Silicon Interlaken IP also provides the following feature set as part of the standard IP functionality:

  • Support for 256 logical channels
  • 8-bit channel extension for up to 64K channels
  • Independent SerDes lane enable/disable
  • Support for SerDes speeds from 3.125Gbps to 56 Gbps
  • Configurable number of lanes from 1 to 48
  • Flexible user interface options:
    • 128b: 1x128b, 2x128b, 4x128b, or 8x128b
    • 256b: 1x256b, 2x256b, 4×256, or 8x256b
  • Programmable BURSTMAX from 64 bytes – 512 bytes
  • Programmable BURSTMIN from 32 bytes – 256 bytes
  • Simultaneous In-band and Out-of-Band flow control
  • Programmable calendar
  • Built-in error detection and interrupt structures
  • Configurable error injection mechanisms for test-ability

“Open-Silicon’s Interlaken IP Subsystem delivers the bandwidth scalability and performance we require for various artificial intelligence applications that require high speed inter-node connectivity. The Interlaken IP subsystem is extremely configurable and robust, which enables the high-bandwidth efficiencies required for deep learning SoCs.”-Open-Silicon Customer

Since 2007 Open-Silicon’s Interlaken IP has been deployed in several different tier-1 networking and computing customer products. Many of these products are shipping in production today in the latest technology nodes in multiple foundries. The unique flexibility and configurability built into Open-Silicon’s Interlaken core meets not only today’s technological requirements, but remains fully compatible with older designs.

Want to get a budgetary quote for Interlaken ASIC? Please fill out the Design Requirements Form.

About Open-Silicon
Open-Silicon is a system-optimized ASIC solution provider that innovates at every stage of design to deliver fully tested IP, silicon and platforms. To learn more, please visit www.open-silicon.com

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Samsung Memory is easy come easy go but for how low?

Samsung Memory is easy come easy go but for how low?
by Robert Maire on 07-29-2018 at 8:00 am
Categories: Semiconductor Advisors, Semiconductor Services
6 Comments

Lam Research (LRCX) reported a great June quarter coming in at $3.126B in revenues and $5.31 in EPS easily beating the street’s $3.06B and EPS of $4.94. However no one will care as guidance for the September quarter is for $2.3B in revs and EPS of $3.20, way, well below the already downward revised estimates of $2.77B and $3.88.

As we had suggested in our preview notes, most analysts had underestimated the extent of the down turn in business. Guidance is well below even the lowest estimate on the street of $2.55B in revs and EPS of $3.53. We had projected a 25% decline which is exactly what management is guiding to.

At this point our thoughts turn to how long the down cycle will last and how much further down it will go?

This begs the question as to whether the slow down started by Samsung will spread to other memory makers and if foundry/logic will recover?

We think that most analysts will again underestimate the length of the down turn. In our years watching the industry we can’t think of very many downturns that were only one quarter or two quarters in length which suggests that we won’t get a recovery until 2019 at best. We highly doubt that Samsung would hit the breaks so hard for only a one or two quarter delay as the underlying issues are longer than that.

We would imagine that other memory makers will be wondering about their capex spending as well. We are in an uncertain period with many variables many of which are negative.

September low point or trough?
Management stated that it viewed the September quarter as the low point for the year. We are somewhat dubious of this given the history of the industry and our view that it seems strange for Samsung to hit the brakes so hard if they were just going to start spending again in a quarter or two.

Perhaps business from other customers can be pulled in such that some of the Samsung shortfall is made up. Management was careful not to predict timing of an uptick or length of the downturn.

How long the down turn?
If September is the “trough” the next question is how long do we stay at the trough? Its clear that there were push outs out of the September quarter and push outs out of 2018 into 2019.

We could be looking at a flat December quarter versus September with a recovery some time in 2019.
One issue we have is that logic/foundry has not been strong and in fact has been weak and not likely to make up for any memory weakness.

We listened very closely to the call and management carefully avoided suggesting an up December quarter but instead talked about long term generic positive platitudes.

There is no specific evidence that points to a recovery at this point but management has planted a flag in the ground to “call” a bottom (if only for 2018).

Single digit WFE growth
It now looks like 2018 WFE capex growth will be in the single digits. Much of this number will be determined by H2 performance which is obviously down in September but unknown beyond that. Its still too early to call 2019 and management also refrained from that prediction.

The stocks
We could see a relief rally as management’s spin is that the worst is behind us. We would caution that just as this downturn was a surprise so could we be surprised by either another leg down or a longer than expected time to recovery.

We are very dubious about those that will suggest that this is only a one quarter blip that we will quickly recover from as that is not anywhere near the norm for the industry and seems to belie the sharpness of the downturn.

We remain cautious on the group in general and more specifically memory related stocks. If we saw a big jump in the stock price we might take some money off the table before the euphoria subsides and reality kicks back in….

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Daniel’s #55DAC Trip Report

Daniel’s #55DAC Trip Report
by Daniel Payne on 07-29-2018 at 7:00 am
Categories: EDA, Events

Another year, another DAC, and last month it was #55DAC in SFO and the first thing that I noticed was that the event was no longer located in the traditional North or South Halls, rather we were in the smaller, Moscone West on two floors, almost like a 3D FinFET. Checkin to get my badge was highly automated and oh so fast, well done.
Continue reading “Daniel’s #55DAC Trip Report”

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1-on-1 with Anirudh Devgan, President, Cadence

1-on-1 with Anirudh Devgan, President, Cadence
by Tom Dillinger on 07-27-2018 at 12:00 pm
Categories: Cadence, Events, Prototyping

At the Design Automation Conference, no one is busier than an EDA company executive — conference panels, product launch briefings, customer meetings, and corporate dinners all place considerable demands on their time. I was fortunate enough to be able to meet with Anirudh Devgan, President of Cadence, at the recent DAC55 in San Francisco. His insights into the challenges and opportunities ahead for the EDA industry were most enlightening. Below is a summary of our brief Q&A discussion.

What big challenges are customers currently facing? How is Cadence positioned to address these challenges?

Anirudh said, “There are three traditional areas that customers continue to emphasize. First is PPA and design productivity. We continue to invest significantly in point tool development, building upon our parallel processing architecture. This applies across the product portfolio. Tool developers are focused on improvements to the quality of results and tool throughput.”

“The second area of emphasis is verticalization. Many customers seek to leverage our vertical design platforms. We provide broad platform support for packaging tools, analog/mixed-signal and custom design, and digital implementation.”

“And, the third area focuses on a system view. There are two axes to chip-package-system (CPS) design. One axis represents the electrical and mechanical analysis requirements of complex product designs. We have established a partnership with MathWorks, to provide unique and differentiating analysis capabilities between MATLAB and Simulink with Cadence AMS and PCB platforms. The other CPS axis relates to system software verification – our Palladium emulation and Protium prototyping platforms provide the requisite system software validation throughput.”

(For more information on the Cadence-MathWorks integration, please follow this link.)

In addition to these three areas, what are other key initiatives underway? There’s lots of buzz here at DAC about machine learning (ML), both the hardware design opportunities for different end markets, and the potential for ML optimizations within EDA platforms.

Anirudh replied, “ML will be the mother of killer apps. The market opportunities are tremendous. Consider that Google and Facebook are essentially ad companies, applying their expertise in search engines to transform a significant share of the $300B Total Addressable Market (TAM) to online advertising. The TAM for the automotive industry alone exceeds $3T, for which there are a multitude of ML applications.”

“In my opinion, there are three main pillars in science – the science of place, the science of pace and the science of pattern, or the 3Ps – which, throughout the years has followed and been enabled by advances in mathematics, physics, and more recently, computing. The science of place evolved from the understanding of the principles of advanced geometry and lasted for centuries. The science of pace is built upon the introduction of differential calculus with the corresponding understanding of dynamic systems. We are entering the onset of the science of pattern. Our ability to identify and learn from information patterns, and then adapt systems accordingly, will have an indelible impact on society. ML will be the enabler for this transition in industrialization.”

How has the resurgence of ML impacted R&D at Cadence?Anirudh highlighted, “We are embedding optimizations within our tools – commonly referred to as ‘ML inside’. For example, we are realizing PPA improvements within our Innovus implementation platform, while maintaining the same user/flow interaction.”

“We are collaborating with customers on ‘ML outside,’ to realize productivity and throughput improvements in their flows.”

What are some of the new ML areas you’re pursuing?

Anirudh said, “The opportunities for ML optimizations in the area of HW/SW co-design and verification are great.”

There’s also lots of buzz at DAC about the availability of cloud-based computing resources for EDA applications. Cadence made a major announcement, identifying multiple available environments – the Cloud Passport model (customer-managed), the Cloud-Hosted Solution (Cadence-managed), and the Palladium Cloud offering. I know we’re about out of time – can you briefly review these cloud opportunities?

Anirudh summarized, “For some time, cloud resources have been a boon to managing the IT infrastructure for many companies who have migrated HR and Finance operations. We knew our investment in a new tool architecture enabling parallel processing and distributed computing would be a great fit for cloud resources. We have collaborated with Amazon, Microsoft, and Google to enable our ecosystem on their cloud platforms.”

“Security is obviously a key concern to customers evaluating a transition of some of their workload to the cloud. We evaluated the security features and partnered with TSMC to conduct extensive security audits, which led to an endorsement in our announcement.”

“We currently have customers who have adopted either the Cadence-managed or customer-managed resources model as well as the Palladium Cloud solution.”

Indeed, the confirmation of foundry support for a cloud model should hopefully alleviate any anxiety about data security. I meant to ask a few more questions about the cloud announcement, such as “How should customers evaluate the costs and ROI of transitioning workload to the cloud?” and“Are customers investigating thecloud-based insurance for risk management?” . But alas, Anirudh had to depart.Our discussion left a strong impression on me, to wit:

  • Execution of the EDA computational workload on the cloud is a solved technical/security issue. The transition of a percentage of the overall computational workload – or perhaps to support a “burst” mode demand near tapeout – is an economic decision.

 

  • The dual axes of ongoing PPA and throughput improvements with ‘verticalization’ of HW/SW system design and verification requirements present tremendous opportunities for EDA growth.

and,

 

  • ML may indeed be the “mother of all killer apps.”

To paraphrase a Chinese philosophy, “We are indeed living in exciting times.”

-chipguy

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Stubbornness Captures an Entire Disruptive Technology and Leads to an Academy Award

Stubbornness Captures an Entire Disruptive Technology and Leads to an Academy Award
by Daniel Nenni on 07-27-2018 at 7:00 am
Categories: Wally Rhines
4 Comments

This is the eighth in the series of “20 Questions with Wally Rhines”

In 1972, I joined TI and was assigned to work on a new contract that had just been awarded and badly needed staffing. The U.S. Department of Defense had decided that solid-state charge-coupled device (CCD) image sensors were going to be a strategic technology and they formed a joint services program under Larry Sumney (who later became CEO of the Semiconductor Research Corporation for more than thirty years). Fairchild had hired Gil Amelio from Bell Labs and was promoting buried channel technology because of its high efficiency, i.e., by using ion implantation to shift the minimum of the electrical potential to store charge below the surface of the silicon, any losses due to surface state interactions were minimal. Meanwhile, RCA was a clear contender in this emerging business because of their experience with video cameras and associated technology (as was Sony, but Sony could not be funded by the U.S. DoD).

TI was desperate to be included in the contract shootout, so they proposed a totally different approach, building the CCD on a silicon wafer and then thinning the devices from the back side to about a 25-micron thickness. This approach avoided the losses associated with shining light on the front side of the device where polysilicon and metal interconnect interfered with light transmission. The CCD thinning technology was relatively simple. We used wafers with a 25-micron thick, lightly doped p-type epitaxial layer on top of a heavily p+ doped substrate. The p-layer served as an etch stop leaving the 25-micron paper-thin layer. TI’s proposal looked good to the Navy’s Night Vision Lab for use in “Starlight Scopes” and, at the last minute, TI was added to the contract. Today, virtually all solid-state imagers are illuminated from the back side of the silicon but that approach really didn’t take off for thirty more years.

Meanwhile, Dean Collins, who ran the CCD Imaging Branch was able to promote the technology to other branches of the government, and lots of additional funding was generated for TI. One particularly difficult contract called for building a moving target indicator that would store and compare successive images. Larry Hornbeck took on the task but stubbornly refused to fabricate the device as originally proposed. Instead, he pursued what he called a stratified channel CCD architecture, the first-ever CCD to have the capability for storing two overlying charge-storage and transport channels. With the assistance of people like Ken Bean (discussed in the last blog) for the epitaxial process development and Jerry Hynecek (inventor of TI’s virtual-phase CCD) for the modeling task, Larry proved the concept with backside illumination of thinned, packaged devices.

Dean sold another program to the DoD, this time for a “solid state light modulator” that again relied on TI’s thinning expertise. It used a hybrid manufacturing process to produce a frontside, deformable mirror spatial light modulator, with backside CCD-addressing. The deformable mirror was a continuous sheet of a metalized polymer membrane. Once again, Larry came up with a different approach, consistent with his future habit of taking on the management to pursue approaches that ultimately proved to be superior and more manufacturable on the path to his “Digital Micromirror Device” or DMD. Larry was convinced that creating arrays of individually-addressable cantilever micromirrors along with a monolithic manufacturing process would solve problems of defects in the array and lead to much improved optical performance. By this time, I had taken on the job of President of the Data Systems Group and Tom Stringfellow, who managed the Peripheral Products Division of the Group, began funding Ed Nelson to support a potentially revolutionary approach to printing using the digital micromirrors. George Heilmeier, who was one of the first senior TI managers to be hired from outside the company, became VP of Research for TI and supported Larry for the chip development. By 1986 Larry had developed and patented the first practical methods for manufacturing high-density arrays of micromirrors on an integrated circuit in a conventional wafer fab. This IP and its sound reduction to practice by Larry served as an initial barrier to potential competitors who would have immediately started developing their own version of the digital micromirror device, once it was publicly disclosed in 1988. Thirty-one years after the invention of the digital micromirror device in 1987, TI is still the only manufacturer of this disruptive technology, a highly unusual, and possibly unique, example in semiconductor history.

Larry made a pivotal decision in 1987 to attach the micromirrors to torsional suspensions and actuate them into contact with rotation stops. This made it possible to manipulate light with the precision of time division by pulse-width modulation, increased the optical efficiency and reduced the address voltage. And so, the digital micromirror device (also DMD) was born (U.S. Patent 5,061,049, Spatial Light Modulator and Method, Inventor L.J. Hornbeck). The DMD became commercially known as the DLP chip.

The tiny mirrors of this device assumed a “1” or “0” position and pulse width modulation was applied to control the pixel intensity, a method that required extensive algorithmic development to produce high quality projected images. Numerous other problems had to be solved, such as the gradual increase in surface stiction to the point where a mirror would stick in a “1” or “0” position, a problem Larry immediately addressed with a novel, electro-mechanical release mechanism and in 1990 with a surface treatment that he developed (despite his claim that he hated chemistry).

Through all this, the Semiconductor Group didn’t want to take the product to production. Potential applications, like projection TV, would require major investments with questionable business benefit since the light modulator component was a small part of the total system cost. But TI, with some government help, provided enough funding to keep it alive and Larry’s persistence provided the momentum.

And then, in the late 1980s, Jerry Junkins became CEO of TI. Jerry was looking for a semiconductor project with system implications that could make a real difference to the company. Jerry’s background was running the defense business of TI and the DMD looked good to him. So, he redirected the staff of an older (four inch) wafer fab that was destined to be shut down and totally dedicated it to working out the bugs in the DLP chip.

TI built a total portfolio of know-how, software, CMOS-based manufacturing technology and intellectual property to lock up an amazingly disruptive technology. The entire motion picture industry distribution structure was totally changed as its 115 year old projection systems were replaced by “DLP Cinema” technology and software based distribution of motion pictures. TI approached other applications including printing and home projection systems with a solutions approach that included the basic DLP component, algorithmic development, manufacturing, and application engineering. The revenue approached $1B, and companies like Samsung and RCA introduced televisions based upon the DLP because of its extremely bright, sharp colors.

Ultimately, Larry Hornbeck, the innovator and developer of the technology, was nominated for and received an Academy Award of Merit (Oscar statuette) in 2015. Most interesting to me, however, is the fact that TI kept the DLP program alive for almost twenty years before any real revenue was realized. This wasn’t the only example of persistence at TI, accompanied by tolerance for inflexible innovators, and it is part of the reason that TI is the only semiconductor company that has ranked among the ten largest since the 1950s.

The 20 Questions with Wally Rhines Series

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Low Cost Power NB-IoT Solution? Fusion F1 DSP based Modem!

Low Cost Power NB-IoT Solution? Fusion F1 DSP based Modem!
by Eric Esteve on 07-26-2018 at 12:00 pm
Categories: Cadence, IoT, IP

Supporting NB-IoT requires low cost (optimized silicon footprint) and ultra-low power solution to cope with IoT device requirement. Cadence Fusion F1 DSP IP has been integrated in modem IC by two new customers, Xinyi and Rafael, gaining traction in NB-IoT market. These design-win builds on previous momentum: software GPS solution from Galileo announced at MWC 18 (Barcelona) and CommSolid NB-IoT modem, at MWC 17 (before CommSolid acquisition by semiconductor company Goodix in Feb 2018).


Fusion F1 DSP architecture has been optimized to offer Ultra-low Energy for IoT Applications. These applications are multiple, as they allow connecting “things” and processing whichever data the thing is capturing. The DSP is intended for sensing, wake-up processing, audio voice speech processing and support communication with the outside world. The communication protocol can be NB-IoT, Wi-Fi HaLow or GNSS. Speech processing capabilities range from speech recognition or pre-processing to audio playback. Wake-up processing supports Voice trigger, Face trigger or Gesture trigger. Sensing can be pedestrian dead reckoning, biometric monitoring or sensor fusion.

Tensilica® Fusion F1 DSP Base Architecture is Xtensa Base ISA, offering Dual-issue, VLIW processor based on HiFi 3 DSP architecture VLIW, which is only used when required to save power consumption. MAC support is highly flexible, from Single 32×32, Dual 32×16, Dual 24×24 or Dual 16×16. To reduce MAC latency, an optional mode allows certain instructions to have a reduced latency to save power and area.

The Fusion F1 DSP core is above pictured and the green box is the core basis. Because Tensilica want to address various applications, IoT and even more, the flexibility has been the driver for the architecture definition. The 7 blue boxes (FPU, AVS, AES-128, 16-bit Quad MAC, Viterbi, Soft Bit Demap and Bit Manipulation) are proposed as pre-verified and proven option. A chip maker can really optimize the DSP core definition in respect with the real needs of the application, and minimize the DSP area and power consumption. This flexibility is added to the natural DSP flexibility, as you can use the same core to support the communication protocol (the modem) when active, then switch to support sensor fusion when needed. This strategy is also good for power consumption optimization, which is key for this type of application.

This Fusion DSP can target technology nodes from 55 nm, 40 nm, 28 nm to 22 FD-SOI (all of these sounding good for IoT applications), and obviously smaller nodes when designing to support very complexes platforms.

Tensilica® Fusion F1 DSP Value Proposition is to provide Ultra-low Power Processing for Always-On/Wearables/IoT.

The first goal is to offer leading low power DSP/Control performance. Starting with lowest possible energy for always-on and excellent control code performance (up to 4.61 CoreMark/MHz), Fusion F1 offers efficient floating-point support for sensor fusion and Quad MAC performance for narrowband wireless.

Because IoT systems are multiple, it’s important to provide very good configurability allowing designer to get the right processor immediately. We have listed the pre-verified and proven option, allowing to configure exactly for the targeted applications. In short, it guarantees maximum efficiency and no waste (optimized silicon footprint and cost, smallest possible power consumption).

Because IP strength is also based on the IP ecosystem size, Cadence propose comprehensive software packages (250+ SW packages) offered by 120+ partners. Optimized DSP library with fixed point and float point kernels allows benefiting from the best performance/power compromise.

To support NB-IoT, communications ecosystem support has been emphasized. With Xinyi selecting Cadence® Tensilica® Fusion F1 DSP for their new highly integrated NB-IoT modem, Marconi X1 NB-IoT (Release 13 and Release 14) SoC, based on Fusion F1 DSP. This new modem offers very high-level of integration including an integrated power amplifier (PA), allowing for up to 30 percent reduction in modem cost. Protocol stack for this modem is supplied by Huachang Technology and has been optimized to save 20% on program code requirements.

Rafael Micro has also licenses Cadence® Tensilica® Fusion F1 DSP for Low-Power NB-IoT Modem IC, introducing the RT580 NB-IoT modem IC, which features an integrated RF radio. Important to mention, Rafael selected the Fusion F1 DSP after their benchmark results showed 36 percent lower power and 45 percent smaller code versus a competitive processor core…

The following link to more information about the Fusion DSPs: https://ip.cadence.com/ipportfolio/tensilica-ip/fusion

ByEric Esteve fromIPnest

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Cadence Selected to Support Major DARPA Program

Cadence Selected to Support Major DARPA Program
by Bernard Murphy on 07-26-2018 at 7:00 am
Categories: AI, Cadence, EDA

When DARPA plans programs, they’re known for going big – really big. Which is what they are doing again with their Electronics Resurgence Initiative (ERI). Abstracting from their intro, this is a program “to ensure far-reaching improvements in electronics performance well beyond the limits of traditional scaling”. This isn’t just about semiconductor processes. They want to redefine the way we architect and design/implement, along with the foundations of design, pushing ideas beyond the timeframes that industry will normally consider (they’re looking at 2025-2030 horizons).

In architecture they have two programs: software-defined hardware (SDH – runtime reconfigurable hardware) and domain-specific system on chip (DSSoC – mixing general and application-specific processors, accelerators, etc). In design they have two programs: intelligent design of electronic assets (IDEA – no human in the loop layout generator, runs within 24 hours) and Posh open source hardware (POSH – hardware assurance technology for signoff-quality validation of open source mixed signal SoCs. And finally, materials and integration: 3D-SoC (3DSoC – enable > 50X in SoC digital performance at power) and foundations required for novel compute (FRANC – proofs of principle for beyond von Neumann compute architectures).

DARPA held a summit in San Francisco, 23-25 July, to launch the initiative and announce some of the winning proposals, including a joint proposal from Cadence, NVIDIA and CMU. I talked with Dr. David White (Sr Group Director of R&D at Cadence) who will be running the Cadence part of the program, which Cadence calls MAGESTIC, as PI. David has a strong background in both AI and design. He completed his doctorate in EE/CS at MIT on characterizing semiconductor wafer states using machine learning (ML) and other methods. He later co-founded the DFM company Praesagus, later acquired by Cadence, and for the last ~10 years has been running Virtuoso EAD and is also lead for the Cadence ML task force.

Unsurprisingly, Virtuoso has been leveraging ML for quite a while, so they’re not coming into this cold. And since they’re partnered with NVIDIA and CMU, this is a heavy-hitting team. David says they’ll start with analog. That’s pretty clear – they already have product on which to experiment and build. But remember the goal is ambitious – no human in the loop to generate layout – so this will take a bit more than polishing.

Interestingly, they are including intelligent PCB place and route in their goals. In placement, they will use deep learning to evaluate the possible design space and placements, select an optimal set based on analytics and previous learning, run the placement and feed metrics back to the learning engine. They’ll do a similar thing in routing, again feeding back the fitness of result to the DL engine.

David expanded further on the expected flow for custom IC design, I would guess because the foundations of this are already clear through their Virtuoso EAD and advanced node place and route capabilities. The key challenge here is to address uncertainty in design intent; how can you remove the human from the loop if what the human wants isn’t clear? We know what we want, but in a general and not fully-specified sense, and we expect to have it adapt as implementation progresses. This is where ML combined with analytics has promise; to capture implicit intent and best-practices based on what is explicitly known but also on what can be observed from legacy designs.

He illustrated their approach with a custom layout example. Locally a designer can run fast extraction and electrically-aware assistance, fast RC analysis, static EM analysis and so on. From this they can switch to a more intensive electrically-driven optimization where they can explore design alternatives aligned with intent (captured as design constraints), each of which is graded using cost functions. All of this is of course massively parallelized (server farms, clouds, etc) to get quick turn-around. This whole subsystem interacts with an intelligent tools subsystem for ML, analytics and optimization, the intelligent tools both observing the outcome of analyses and optimizations at the designer level and feeding back recommendations and refinements. Obviously this flow still has a human in the loop but you could imagine through learning, refinement and new capabilities, the need for that human could be minimized or even eliminated in some cases.

We wrapped up with a couple of questions that occurred to me. How do you bootstrap this system? David said that this is a common challenge in such systems; the standard approach is to start with baseline models, while allowing those models to adapt as they learn. Does he expect that system behaviors will diverge when applied to different applications? Yes, certainly. Baseline models won’t change but tools should tailor themselves to provide optimal results for a target application. Which raises an interesting point they may consider – might the tool be able optimize across multiple target applications, to build a product to serve multiple markets?

Kudos to Cadence for landing a role on this ambitious initiative. I’m sure the rest of us will also benefit over time from the innovations they and other partners will drive. You can learn more about the DARPA initiative HERE and Cadence’s MAGESTIC program HERE.

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Autonomous Driving and Functional Safety

Autonomous Driving and Functional Safety
by Tom Dillinger on 07-25-2018 at 12:00 pm
Categories: EDA, Siemens EDA

The timelines proposed by automobile manufacturers for enabling fully autonomous driving are extremely aggressive. At the recent DAC55 conference in San Francisco, I attended a panel discussion on Functional Safety issues for assisted and autonomous driving, sponsored by Mentor Graphics. I also had the opportunity to chat with Bryan Ramirez, DVT Strategic Marketing Manager at Mentor, about the progress, opportunities, and challenges in addressing these issues. The insights shared by Bryan and the panel were eye-opening (to me, at least).
Continue reading “Autonomous Driving and Functional Safety”

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Optimization and Reliability for FinFET designs at #55DAC

Optimization and Reliability for FinFET designs at #55DAC
by Daniel Payne on 07-25-2018 at 7:00 am
Categories: Events, FinFET, IP, Moortec

TSMC is the leading foundry worldwide and they make a big splash each year at the DAC exhibit and conference, so I stopped by their theatre area during the presentation from IP vendor Moortec to see what’s new this year. Stephen Crosher was the presenter from Moortec and we had exchanged emails before, so this was the first time that we had a chance to meet in person.


Designing an SoC for use in a system is a complex task these days, and even premier design companies like Apple have reported performance issues with their newest MacBook Pro laptops because as they were warming up under high loading the fans came on to cool the system off and then the CPU frequency was throttled to lower the temperature, but it was throttling back too much and actually performing slower than the previous CPU generation used. Fortunately for Apple they will issue a software fix to correct the clock throttling issue. Modern day SoC projects require that the design team have a plan for an optimized system that is also reliable.


MacBook Pro overheats, throttles frequency too much. Source: Apple

Some of the challenges in FinFET design are well known:

  • Higher thermal density
  • IR drop and PDN (Power Delivery Network) issues
  • Noise between coupled signals and injected into the substrate
  • Reaching timing closure

With each successively smaller process node we enjoy the benefits of increased gate densities, but at the expense of also increased power densities that can cause reliability issues. Narrower and higher-resistance interconnect layers impact timing to a greater degree and increase the variation effects. Add up all of these issues and it makes reaching timing closure even more difficult.

The Moortec approach to these challenges is to provide monitoring IP placed strategically within certain regions of an SoC, where the PVT sensors communicate to a controller that can then perform actions like scale the voltage, or throttle clock frequencies in order to have a reliable chip. Experts at Moortec have engineered this IP across multiple process nodes:

  • 40nm
  • 28nm
  • 16nm
  • 12nm
  • 7nm

Some of the benefits of using this pre-built monitoring IP in your next chip include a reduced risk of failing to meet specs, an improved yield at the foundry, better reliability and chip lifespan, and no up-front development costs to design and qualify your own IP. With the Moortec IP embedded you can better implement dynamic or adaptive schemes like DVFS (Dynamic Voltage Frequency Scaling) or AVS (Adaptive Voltage Scaling).

Many chip segments will benefit from embedded monitoring:

  • Datacenter – thermal management, high gate densities, leakage currents, CPU temperatures
  • Consumer – process variability, thermal management, localized process variability
  • Automotive – reliability and thermal management, real-time monitoring throughout vehicle lifetime
  • IoT – edge devices that sense and monitor, manage multiple supply levels to meet power specs

Moortec has been an IP Alliance Member with TSMC since 2010, starting at the 40nm process node, and in 2016 they received a partner of the year award from TSMC. At DAC there was news from Moortec about supporting the 40nm ULP CMOS technology, useful for the IoT marketplace. It was fun to meet the Moortec team in SFO and see their customer list continue to grow with tier one clients in diverse industries.


Moortec team at DAC in SFO

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About Moortec
Established in 2005, Moortec provides compelling embedded subsystem IP solutions for Process, Voltage & Temperature (PVT) monitoring, targeting advanced node CMOS technologies from 40nm down to 7nm. Moortec’s in-chip sensing solutions support the semiconductor design community’s demands for increased device reliability and enhanced performance optimisation, enabling schemes such as DVFS, AVS and power management control systems. Moortec provides excellent support for IP application, integration and device test during production. Moortec’s high-performance analog and mixed-signal IP designs are delivered to ASIC and System on Chip (SoC) technologies within the consumer, mobile, automotive, high performance computing and telecommunications sectors. For more information, please visit www.moortec.com, follow us on Twitter and LinkedIn.

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Automotive is setting the goalposts for next generation designs

Automotive is setting the goalposts for next generation designs
by Tom Simon on 07-24-2018 at 12:00 pm
Categories: Automotive, EDA, Events, Synopsys

Automotive applications are having a tremendous influence on semiconductor design. This influence is coming from innovations in cloud computing, artificial intelligence, communications, sensors that all serve the requirements of the automotive market. It should come as no surprise that ADAS and autonomous driving are creating the majority of the push in each of these areas. At DAC this year in San Francisco there was plenty of buzz about all things automotive. I was able to attend a very informative lunch event hosted by Synopsys – “Automotive Drives the Next Generation of Designs”.

The event was kicked off by Synopsys VP of Automotive Business Development, Burkhard Huhnke. There were presentations by each of the four panel members, representing a wide swath across the industry. First off there was Jonathan Colburn, Distinguished Engineer at Nvidia. He was followed by Dr. Akio Hirata, Chief Engineer at Panasonic. Next up was Hideki Sugimoto, CTO at NSI-TEXE. Last came an informative presentation by Tom Quan, Director of OIP Marketing at TSMC. The panel included chip makers, IP providers and foundry representation.

There were several important themes from the talks. Initially Burkhard spoke about the motivation for ADAS and Autonomous driving. Apparently 84% of accidents are caused by human error. So, while we cannot completely eliminate all these accidents with automation, this is low hanging fruit for improving safety. With over 100 people a day being killed in car accidents, reducing the accident rate is a goal we should pursue. In addition, there is a strong economic argument for reducing accidents, they have direct and indirect costs that go into the hundreds of billions of dollars per year.

Several speakers pointed out independently that the need for automation is greatest specifically for the least complex and most complex driving tasks. These are the occasions where humans perform most poorly. An example of a complex driving task is merging onto a busy freeway or turning at intersections. The least complex driving situations are those where distraction or loss of attention can occur, such as on long-distance trips or in traffic jams.

Nvidia, Panasonic and NSI-TEXE all talked about the changing needs for computing. Heterogeneous computing is universally considered the optimal solution for training and recognition functions. NSI-TEXE sees a large role for flow computing in offering the quickest response time for emergency events or system failures. Nvidia, as you might expect, touted the advantages of mixing GPUs with CPUs. One interesting twist that Jonathan mentioned was that Nvidia uses some of their gaming technology to modify training data to alter the conditions and create realistic, but hard to recreate training scenarios. It’s a given that the quantity and quality of training data has a big effect on the quality of recognition operations. Using real world physics, they can create virtual training data. As a result, Nvidia can generate massive numbers of hours of training data that simply would not be available in any other way.

In the TSMC talk, Tom Quan spoke about their efforts to support the automotive market. By 2020 the electronics in most cars will shift from the passive safety, infotainment and vehicle control categories to an expanded set that also includes many new functions. There will be big changes in autopilot and ADAS. New communications capabilities will include 4G/5G, V2X and over the air update. The help the environment and improve efficiency there will be greener engine controls for EV and HEV. To help drivers, there will be natural interface for voice command, gesture control and recognition tasks that could include driver alertness detection, personalization based on face recognition. These new categories will incorporate more and more TSMC technologies.

Infotainment is using 28nm and 16nm, ADAS and partial autonomous is using 16nm, and highly autonomous will require 7nm which will be prevalent after 2020. One particular area of interest for TSMC in the automotive market is sensor technology. Many cars already have 7 to 21 sensors, including multiple LIDAR, camera, radar, ultrasound and NIR camera units. Higher levels of automation will see the need for sensors to expand significantly. NSI-TEXE pointed out that the sensor data will require increased processing to extract every bit of useful information to make autonomous driving systems more reliable. Key TSMC technologies used in the sensor domain include MEMS, eNVM and high voltage processes such as BCD.

I can really only skim over the interesting content from this talk. Fortunately, Synopsys has posted a video of the lunch session. I highly recommend watching the entire session for more insights into what Synopsys, TSMC, Panasonic, Nvidia and NSI-TEXE are doing in the automotive space. Every time I attend a session like this on the topic of automotive electronics I come away with a better understanding of this rapidly changing area.