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I Finally Understand Brexit

I Finally Understand Brexit
by Roger C. Lanctot on 03-17-2019 at 7:00 am
Categories: Automotive

I have gazed across the Pond in bafflement over Brexit until two days ago. I now grasp the depth and breadth of British anxiety over political and legal ties to Brussels and it boils down to regulatory over-reach.

Yesterday, the European Commission announced that it had adopted new rules “stepping up the deployment of Cooperative Intelligent Transport Systems (C-ITS) on Europe’s roads.” What the commission has actually done is to create a de facto mandate of a 20-year-old Wi-Fi-based wireless technology (dedicated short range communication or DSRC) for collision avoidance and toll paying applications in a manner likely to cost thousands of lives and reverse decades of vehicle connectivity progress.

This is only the latest chapter in the EU’s misguided efforts to use its regulatory power to influence automotive design decisions. A more than decade-long effort to require automatic crash notification technology resulted in an eCall mandate which came into force nearly a year ago requiring all new type approved cars in Europe to come with a module capable of directly calling the nearest public service access point (PSAP) to report a crash – in the event that one has occurred.

The EU eCall mandate placed an undue financial burden on car makers and the PSAPs to support an application based on an outmoded technology specified by the Commission. The objective was to save 1,200 lives annually. The equivalent of this EU mandate would be, in the U.S., for the Federal government to require all cars be outfitted with OnStar. It’s clear to me that neither consumers nor auto makers would welcome such a mandate – in spite of its life-saving potential.

The same sentiment applies to the ITS-G5-related vote this week. The EC wants to mandate a 20-year-old Wi-Fi technology for collision avoidance, toll payment and other applications – creating another financial burden with little anticipated investment return.

There is a lot at stake. The EU, generally and admirably, has half the annual per-100,000 miles fatality rate as the United States. With 1.2M people dying on highways annually on a global basis, preserving that life-saving leadership is essential.

One must ask, though, at what cost? Estimates of the cost of full deployment of DSRC technology in the U.S. run to $100B. Is the EU prepared to take on that burden? A cellular-based solution would offload much of that expense onto the existing wireless carriers, which are capable of recapturing those investments from resulting commercial revenue.
China has a highway fatality rate several times the level of the U.S. China is opting for 5G and C-V2X technology for collision avoidance and other safety and non-safety-related applications. The U.S. Department of Transportation has shifted to a technology agnostic stance, while adopting cellular technology for other safety-related applications.

In spite of growing global ambivalence, if not hostility, toward DSRC-based ITS-G5, the EC saw fit to make a decision likely to have the impact of a mandate. That mandate, will require that cellular modems find a way to communicate with DSRC systems if they want to access prioritized ITS safety messages.

The scope of the EC’s malpractice and malfeasance is enough to cause one to forgive the more than 15M British citizens that voted to Brexit. First eCall. Now ITS-G5. Please, show me the way out of this regulatory-obsessed regime.
How can the current trajectory be reversed?

According to the EC announcement: “The Commission decision takes the form of a Delegated Act. The publication of the Delegated Act is followed by a two-month period during which both the European Parliament and the Council may oppose its entry into force.”

In the words of one observer: “There is very little room for maneuver at this point. Opponents might prepare to trigger the review clause 33 to propose a new technology, but this will eventually require a “backward compatibility” with ITS-G5.”

Status:
European Parliament (EP) text has been officially submitted. EP has now two months to raise an objection on the file, otherwise the Delegated Act is adopted.

Procedure to raise an objection:

An objection against the Delegated Act can be driven and raised via:

1. TRAN Committee – members of the committee vote with simple majority

2. One political party (e.g. EPP) – irrespective of its size – the members of one political group support a motion for objection

3. Alignment of minimum 38 MEPs – (from different parties/irrelevant if members of TRAN) support a motion for objection

4. If (1) or (2) or (3) is successful – text goes for vote in the EP Plenary – to pass the motion for objection 376 MEPs should vote in its favor

  • Next meeting of TRAN Committee when the Delegated Act steps will be decided is April 8.

  • The Member States in the Council should vote with qualified majority in support of the motion to object against the proposal for Delegated Act – this means out of 28 ministers and these 16 ministers should represent at least 65% of the total EU population.

Observers of the European Commission might be distracted by ongoing Brexit debates or might consider the organization somehow irrelevant or unworthy of their attention. One thing is clear: The European Commission is neither irrelevant nor unworthy.

The organization has the power to make decisions with lasting impact both negative and positive. The most dangerous of those decisions are the ones specifying, regulating or mandating particular technologies.

The process leading up to the mandate for eCall created massive uncertainty in connected car technology deployments for European auto makers resulting in delayed deployments, lost investments and time and, certainly, additional loss of life. It also resulted in the introduction of the so-called “dormant SIM,” a device that will only connect in the event of a crash.

The run up to the de facto ITS-G5 mandate similarly injected confusion and delay of new technology adoption in the automotive market. The outcome is likely to be two parallel vehicle-to-vehicle technology paths being implemented simultaneously – ITS-G5 and C-V2X – with all of the cost, complexity and delay that that implies – and a corresponding and continuing loss of life.

So, yes, I finally understand Brexit. I get it. The EC can’t seem to stay in its lane when it comes to regulating automotive wireless technologies. Further participation in the EC is pointless and resistance is futile. Ergo Brexit.

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China Innovation Forum and ES DESIGN West

China Innovation Forum and ES DESIGN West
by Daniel Nenni on 03-15-2019 at 7:00 am
Categories: ESD Alliance, Events, Semiconductor Services

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I had a chat with Bob Smith, Executive Director of ESD Alliance, about the upcoming SEMI conference in China. More than 100,000 people are expected to attend which is beyond my comprehension. SEMICON in San Francisco is maybe 20,000 people which is the largest conference I attend. I’m not sure if the Design Automation Conference ever hit 20,000 but now it is under 10,000. As you can imagine, Bob and staff are having a good time since joining SEMI last year, absolutely.

Bob also mentioned that Registration is now open for the inaugural ES Design West conference which is co-located with SEMICON West in San Francisco July 9-11. This is now the most comprehensive semiconductor/electronics conference I know of and the exhibitors are already lining up (Cadence, Synopsys, Mentor, etc…). Keynotes include one of my favorites Aart de Geus (Synopsys) and Lisa Su (AMD) amongst a host of others.

On a side note take a quick look at this SEMI sponsored “Contact Protocall” trailer and let me know what you think in the comments section.

Back to China, Bob did some digging in their MSS database to see what the trends for EDA and IP look like and came up with the following observations:

  • Between 2015 – 2018 combined sales of EDA tools and semiconductor IP in China grew at a CAGR of 20%+
  • During the same time period, the overall worldwide growth of combined EDA and IP was about 8%
  • Looking just at EDA during that same time period: China 23% CAGR; Worldwide 8% CAGR
  • In 2018, the estimate is that China will have accounted for roughly 8% of worldwide revenue for EDA and IP sales

I will talk to Bob again when he gets back from China but here is a look at the conference abstract and a link to the conference page. It is interesting to note that I know only two of the 20+ presenters so it is not the same-old-same-old.

Abstract:
SIIP China, SEMI Innovation Investment Platform, aims to be one of the most collaborative and influential investment platform for global semiconductor industry by leveraging SEMI global industrial resources, together with global industrial capital and intelligence. SIIP China: SEMI Innovation and Investment Forum, is one of SIIP China’s brand activities held simultaneously with the annual SEMICON China. Besides the Forum, the SIIP China series include Matchmaking Sessions, Theme Discussions, Regular Industry Investment Gathering and Overseas Delegations.

New applications such as Artificial Intelligence, Cloud Computing, Big Data and IoT are bringing big changes to the semiconductor industry. It is expected that 5G will have even more dramatic effects on our daily lives by its higher speed, bigger capacity and low latency. The global semiconductor industry is entering a major period of transition. Being the biggest integrated circuit consumer market in the world, China has been keeping a two-digit growth these years. The trade friction may have added some uncertainty however we look forward to the promising future from the global perspective. No matter how erratic the external environment is, funds, technology, products and talents have always been the key driving forces for the entire eco-system of semiconductor to grow steadily and healthily.

SIIP China: SEMI Innovation and Investment Forum 2019 will focus on the latest policies, diagnose the current situation of the industry, analyze the capital flows and forecast the future. The New-tech Panel will discuss about how deep learning, big data & cloud computing, 5G and manufacturing will bring dramatic changes to the semiconductor industry and what the perspectives of the China market will be.

In 2018, SEMI completed the integration of Electronic System Design Alliance (ESDA). Consisting of major EDA, IP, and fabless companies, ESDA acts as the central voice to communicate and promote the value of the semiconductor design industry as a vital component of the global electronics industry. The ESDA integration brings key capability and further enhances SEMI’s supply-chain coverage and SEMI’s vertical application platforms such as Smart Transportation, Smart Manufacturing and Smart Data as well as key enabling technologies including AI, 5G, and Machine Learning. During the ESDA Executive Panel, leading companies such as Alibaba, Mentor, Synopsis, Unisoc and Cadence will talk about their cutting-edge technologies.

About the Electronic System Design Alliance
The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner representing members in the electronic system and semiconductor design ecosystem, is a community that addresses technical, marketing, economic and legislative issues affecting the entire industry. It acts as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. Visit www.esd-alliance.org to learn more.

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Traceability and Design Verification Synergy

Traceability and Design Verification Synergy
by Daniel Payne on 03-14-2019 at 12:00 pm
Categories: EDA, General, Perforce

The IC design and verification process can be comprised of many independent point tools, or for more synergy you can have tools that work together by a more synergistic process. We’ve all heard the maxim, “Work smarter, not harder.” A white paper just came out from Methodics on a smarter approach, Traceability for the Design Verification Process, so I’ve taken the time to read the 9 pages and then present my findings. The three activities in electronic systems that can be smartly made to work together are:

  • Requirements Management
  • Design Management
  • Verification Management

When you’re designing something safety critical then you’re likely following a standard like ISO26262 and DO-254, where traceability is part of the FuSa specifications. In a utopian world you could follow a linear process, like:

1. Write requirements

2. Perform design

3. Verify that the design meets requirements

4. Ready for production

In reality, we have iterations between step 3 verification and step 2 design, and even from verification back to a change or clarification of the requirements. Remembering what has been verified and on what version of iteration it happened is critical for a smart work flow, so traceability matters a lot.

At the start of an electronic system design the verification of the design is happening in parallel with the actual design, while later on in the process the design has settled down and stopped changing so there’s a shift to completing all verification work, resulting in bug fixes or performance tweaks in order to meet the specifications. So throughout the verification process a smart flow will be able to track each design release with specific verification results. With such traceability your team can reproduce a bug condition and verify that the design fix now passes all regression tests.

In the first diagram shown above you can see the three inter-related activities: Requirement management, Design management and Verification management. What ties all of these activities together is the Percipient tool, because it’s an IP Lifecycle Management platform (IPLM) that can manage IPs, workspaces and verifications. In Percipient you define a project release and that includes all of the IP being used, plus verification tests and results. This is also called the Bill of Materials (BOM).

With Percipient there’s a traceable path from requirements to both design and verification, so when there’s a change in requirements then you know which parts of the design and verification need to be updated as well. Workspaces are built and managed with Percipient, so it always knows with each release what the top-level IP and all lower-level IP blocks are, along with the dependencies. As your team runs verification tests they are kept track of by this IPLM framework, along with release tracking. Here’s a diagram of a design hierarchy and test frame to show the interactions that are tracked by Percipient:

In the lingo of Percipient all of the design blocks, even new content, are called IPs in the workspace. When a test frame runs then this workspace keeps track of that run and the verification results. Instead of relying on human memory about which tests have been run on each IP or workspace, the Percipient tool is doing the verification tracking for us, leaving kind of an audit trail as shown below:

With this methodology you will know the version of the top IP in your workspace, the user running each test, the status of the test, how much run time it took, and any extra arguments that were passed to the test. Each team member using this tool flow will automatically have their verification activities stored by default, then the results can be retrieved as needed.

The automatic benefit of verification traceability means that you can track which tests were run in each workspace created with each release, and know which engineer ran the test. There’s no ambiguity about what tests have been run and verified on your project.

Let’s say that your team is building an electronic system for automotive use and that you will adhere to the ISO26262 requirements, providing proof about:

  • Known versions of all IP blocks
  • Design content of each IP by version
  • All tests run and passed on all IPs, per version

If it took 10 versions to achieve a stable design that met all of the design requirements, then we know that the “IP Tree” of version 10 has a top-level IP in Percipient with all of the hierarchy and low-level IPs. All IP contents as files and versions are cataloged. Verification records detail all the tests and results that passed with version 10. This list can be output from Percipient as a PDF document using a standard format like DITA.

Conclusion
Work smarter, not harder. When it comes to designing electronic systems for FuSa markets you should consider using a tool like Percipient because it connects together requirements management, design management and verification management in a work flow that doesn’t slow down your engineering staff. You get traceability automatically with Percipient, so both design engineers and verification engineers are working toward a common goal by using a single source of truth.

Read the complete White Paper online here.

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Silvaco WEBINAR: Nanometer Library Characterization Challenges and Solutions

Silvaco WEBINAR: Nanometer Library Characterization Challenges and Solutions
by Daniel Nenni on 03-14-2019 at 7:00 am
Categories: EDA, Events

As you may know, Silvaco has done some very clever acquisitions to fuel their unprecedented growth over the last five years. We have a wiki that tracks EDA Mergers and Acquisitions, Silvaco included, and it is the most viewed wiki on SemiWiki.com with 102,005 views thus far.

Silvaco acquired Nangate in March of 2018. NanGate got started in 2004 by a group of engineers from Vitesse and Intel. The technology and market idea was to address and solve the inherent shortcomings of standard cell based design as compared to full custom. Anyone having tried to push the performance of a standard cell design knows the frustration… if only I had a better library or if I could just have these extra cells made! And for the library team… If I had more time to characterize!

I spent a good portion of my career trying to solve the standard cell challenge working for Sagantec, Prolific (acquired by ARM), and Virage (acquired by Synopsys). In fact Prolific competed directly with Nangate and a company called Cadabra (acquired by Numerical which was acquired by Synopsys).

If creating standard cells was not hard enough, characterizing the cells became even more of a challenge with libraries going from hundreds of cells to thousands. Then came FinFETS and process variation as an even bigger challenge to accuracy and characterization throughput, which brings us to the webinar at hand:

Nanometer Library Characterization: Challenges and Solutions
Designers today see a significant increase in the number of simulations and PVT corners required to an accurate library characterization, including new formats to support process variations, that can be critical at advanced process nodes. This webinar will review the challenges to have accurate characterization results with a fast turnaround time and how Silvaco characterization solutions can help our customers to achieve that. Offering flexible service formats, Silvaco has a complete characterization solution and the expertise to configure, drive and QA the characterization process. We will also cover an introduction of the characterization tool flow, including its new and advanced capabilities.
What attendees will learn:

  • Characterization challenges posed by current demands
    • The increase number of PVT corners and models needed
    • Better ways to meet those demands

     

  • The characterization solutions Silvaco offers
  • Characterization services, tools or a combination of them
  • Characterization and validation flow
  • Advanced flow: The customizable characterization for non-standard cells
  • Overview of Silvaco library characterization tool, Viola
  • The simple requirements for a characterization service

PRESENTER:
Bernardo Culau is Director of Characterization at Silvaco. He joined Silvaco in 2018 as part of the acquisition of Nangate where he had worked for 9 years. At Nangate he developed EDA tools for library characterization and delivered standard cell library IP for multiple foundries and technology nodes. Bernardo holds Computer Engineering degrees from Universidade Federal do Rio Grande do Sul, Brazil and from Grenoble INP, France.

WHO SHOULD ATTEND:
Design and verification engineers and managers looking for solutions to increase efficiency and accuracy while reducing time and costs of standard cell library characterization.

About Silvaco, Inc.
Silvaco is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world’s ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.

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Segmenting the Machine-Learning Hardware Market

Segmenting the Machine-Learning Hardware Market
by Bernard Murphy on 03-13-2019 at 12:00 pm
Categories: AI, Arteris, Automotive, FPGA, IoT, IP

One of the great pleasures in what I do is to work with people who are working with people in some of the hottest design areas today. A second-level indirect to be sure but that gives me the luxury of taking a broad view. A recent discussion I had with Kurt Shuler (VP Marketing at Arteris IP) is in this class. As a conscientious marketing guy, he wants to understand the available market in AI hardware because they have quite a bit of activity in that space – more on that later.

So Kurt put a lot of work into finding every company and product he could that is active in this space, 91 entries in his spreadsheet. This he broke down by company, territory (eg China or US), product, target market (eg vision or speech), implementation (eg FPGA or ASIC), whether the product is used in datacenters or at the edge and whether it is being used for training or inference. I’ll share some interesting observations from the list but not the list itself. Kurt told me he put a lot of work into building this list, so I can’t imagine he be excited about giving it away :cool:.

I want to be clear up front that this analysis is based on companies, large and small, and products, also large and small. It is not based on investment $$ or revenue, underestimating the impact of hyperscalars and a few others like NVIDIA. So this is necessarily an incomplete analysis but still an interesting indicator in terms of how many organizations are chasing AI hardware opportunities.

Let’s start with territories. Kurt found 28 products in China from 20 companies. In the rest of Asia, Japan has just 4 entries and Korea shows just one, KAIST, which I think may reflect difficulty in finding details on Samsung, LG, etc products since I know they are active in AI. North America shows 38 entries from 32 companies and EMEA (Europe, Middle East and Africa) has 20 entries. Bottom line – China, North America and EMEA are all very active and roughly comparable in product and company count, while Japan lags significantly, and Korea probably doesn’t want to share a lot of information.

Breakdown by target market is more challenging since over half fall into a “general” category – they want to sell to all markets. A little more informatively, 12% fall into what ARM would call infrastructure – from cloud (HPC, servers, storage), to connectivity (5G), mostly in North America, then Japan (who seem to focus their limited investment exclusively in this area) and a few in EMEA. About 10% are clearly targeted to automotive apps, mostly in North America, again with a few in EMEA and one in China. After that, there’s a sprinkling of target markets around smart phone, vision, camera and surveillance, mostly in China with a couple in EMEA.

On implementation, nearly 80% of the solutions are ASIC, 11% are IP and 9% are FPGA, some for neuromorphic implementations. Kurt said he often sees FPGA implementations migrating to ASIC for all the usual reasons. The spread is pretty uniform geographically, at least for ASIC and IP (there are too few FPGA examples to support geographic conclusions).

50% of applications are on the edge and 40% in the datacenter (you might have thought this gap would be wider); the rest are in both edge and datacenter applications. Another useful breakdown is how many products target training versus inference. Unsurprisingly, 60% goes purely into inference and only about 6% purely into training, the balance going into products which address both. In inference, the split is pretty even geographically but almost all the training product interest is in North America.

One last split: on the edge, focus is almost exclusively on inference, whereas in the datacenter the bulk of interest is in both training and inference (pure training remains a small percentage). Why inference in the datacenter? Even for datacenters, the bulk of the hardware opportunity is still in inference per a recent McKinsey report. Not entirely surprising; training needs are compute-intensive but infrequent. Inference needs may be less compute-intensive, but demand is non-stop.

What does all of this have to do with Arteris IP? They play a significant role in ASIC applications in almost all of these domains. They’re in Mobileye and Mobidius, Baidu, Huawei and Cambricon, NXP, Toshiba, Dreamchip, Horizon Robotics, Bitmain, Canaan Creative, Wave Computing and Intellifusion. All AI applications in which their NoC interconnect either connects an AI accelerator to a cache-coherent CPU subsystem (using their Ncore cache coherent interconnect) or deep in the fabric of the accelerator itself in advanced datacenter applications (using their FlexNoC AI package).

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Three things you should know about designHUB!

Three things you should know about designHUB!
by Daniel Nenni on 03-13-2019 at 7:00 am
Categories: Cliosoft, EDA

One of the key growth areas for the semiconductor ecosystem is IP which of course includes IP related EDA software. In May of 2017 design management/collaboration expert (one of my personal favorite EDA companies) ClioSoft announced designHUB[SUP]®[/SUP] for IP management and re-use. Using designHUB, semiconductor companies can easily investigate, evaluate, and integrate internally and externally created IP across geographical company lines:

“There is a paradigm shift occurring within the IP ecosystem regarding IP usage, development and data sharing,” said Srinath Anantharaman, founder and CEO of ClioSoft. “Current products in the market today address IP reuse by web-based cataloging. By using the concept of crowdsourcing, designHUB bridges the gap between the IP developer and the IP user all within a single platform and extends the definition of IP to include SoC sub-systems, documents, ideas, scripts, flows etc. Design related information from various sources is seamlessly integrated into designHUB along with a rich set of reports to provide the relevant information to the designer and management community. Design reuse can now be a reality within a company.” May 2, 2017.


Approaching the two year anniversary, designHUB is now a driving force with ClioSoft customers who just announced record new contracts in 2018:

“There is not just one reuse solution that fits all companies,” said Srinath Anantharaman, founder and CEO of ClioSoft. “Every company has unique requirements, and each company looks for enterprise-class solutions that are configurable for their needs, easy to use, have a low maintenance overhead, a rich set of features, can scale to meet their future needs and be easily adopted within the company. The designHUB ecosystem addresses these needs and continues to be positively received by design team’s year after year.”

designHUB is based on crowdsourcing and leveraging the intelligence of employees within an enterprise. This implies that you can easily create interest/discussion groups within an enterprise wherein you can pose a problem and others can provide you with either a solution or an alternative. All discussions are saved as part of a knowledgebase and can be leveraged by others in the future. Here are the three other things you should know about designHUB:

[LIST=1]

  • Traceability:designHUB redefines the notion of IPs to include semiconductor IPs, documents, flows, scripts etc. It tracks all types of IPs along with their variants and provides detailed reports on where it has been used, what are the open issues against the IP . It also provides notifications as needed if you are following the IPs.
  • Project Dashboard:It enables design teams to set up their own dashboard and upload all project collateral to ensure all designers are on the same page. Project leaders can define their schedules and send either broadcast messages or message individual team members.
  • Independent of Data Management: designHUB comes equipped with a well defined API which enables it to be integrated with any data management system. Currently it supports SOS, GIT, Subversion and Perforce. As a result, it can easily serve as a conduit for IPs, and provides design teams the flexibility of downloading IPs from one data management system and use it another data management system.About ClioSoft
    ClioSoft is the pioneer and leading developer of enterprise system-on-chip (SoC) design configuration and enterprise IP management solutions for the semiconductor industry. The company provides two unique platforms that enable SoC design management and IP reuse. The SOS7 platform is the only design management solution for multi-site design collaboration for all types of designs – analog, digital, RF and mixed-signal and the designHUB platform provides a collaborative IP reuse ecosystem for enterprises. ClioSoft customers include the top 20 semiconductor companies worldwide. The company is headquartered in Fremont, CA with sales offices and distributors in the United States, United Kingdom, Europe, Israel, India, China, Taiwan, Korea and Japan.

Also Read

Data Management Challenges in Physical Design

Webinar: Tanner and ClioSoft Integration

The Changing Face of IP Management

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Synopsys Tackles Debug for Giga-Runs on Giga-Designs

Synopsys Tackles Debug for Giga-Runs on Giga-Designs
by Bernard Murphy on 03-12-2019 at 12:00 pm
Categories: EDA, Synopsys

I think Synopsys would agree that they were not an early entrant to the emulation game, but once they really got moving, they’ve been working hard to catch up and even overtake in some areas. A recent webinar highlighted work they have been doing to overcome a common challenge in this area. Being able to boot a billion-gate design, bring up a hypervisor, guest OS, system services and finally applications, running potentially through billions of cycles, is an accomplishment in itself. But then how do you debug such a monster? Synopsys call this exascale debug because running billions of gates through billions of cycles combines to exascale (10[SUP]18[/SUP]) complexity. Finding and root-causing bugs at that scale takes a lot more help than you are likely used to in IP-based debug.

The Webinar presenter (Ribhu Mittal, Dir of Emulations Applications Engg) listed three main challenges in debug at this scale. First the sequential distance between a bug and the root cause of that bug may be significant – perhaps billions of cycles. This might seem improbable at first but consider how a cache error early in bring-up might result in storing an incorrect configuration value, said value not being accessed until much later in running an app. Cache errors notoriously can lead to this kind of long-range problem. The exascale issue here is how you are going to trace back potentially billions of cycles to who knows what in the design might have caused the problem. How do you intelligently decide what to dump, yet converge quickly through a minimum of iterations?

A second problem is indeterminacy. You want emulation to run as fast as possible with no pauses. At the same time, you have multiple asynchronous testbench drivers interacting with the emulation, say USB and PCI VIPs. When a bug is caught (by an assertion for example), if it was timing-sensitive there is no guarantee that it will appear again when you rerun the test. Changes in system load and environment may make the bug intermittent, which isn’t a great place to start when you want to isolate the root cause.

The third problem Ribhu mentioned is efficiently handling the volume of debug data. Streaming out even a selected set of signals at full speed, then expanding them offline and reading them into a debugger such as Verdi could take hours when you’re working at this scale. That’s before you start to work on where and why you have a bug.

Synopsys have refined a methodology and have put work into optimizing this flow for ZeBu; they cite 3 customers who have used these flows effectively. They recommend starting with a breadth-first search using the checker and monitor collateral you probably already get from IPs and subsystem verification teams. In ZeBu you can call out key signals (such as IP interfaces) from this collateral, before compile, to track system-level behavior; you can monitor these through the complete run at full emulation speed. Use the checkers for coarse-grain isolation of problems and monitors to further narrow the window.

The customer use-cases are particularly interesting. What I got from these is that when you are debugging at the system level, you maybe shouldn’t expect to get down to a root-cause in one pass. At this stage, you’re not finding elementary bugs; you’re more likely finding problems manifesting deep in the software stack. That means you likely want to progressively refine down to a window for much more detailed debug where you might do a full-signal dump. The customer examples shown got there in 2-3 passes, which seems fair given the complexity of the problems they isolated.

For handling indeterminacy, ZeBu offers exact signal record and replay, so on a rerun you can disconnect from the testbench and replay exactly what you ran when you saw the bug. Add to this full save and restart with save at periodic checkpoints; this works with signal replay so you can replay from the closest checkpoint before you saw the bug. Together these provide a deterministic and time-efficient way to isolate and debug those annoying intermittent bugs,

Finally, they’ve speeded up digesting those vast quantities of streamed data for offline debug.
They have fast streaming (2TB/s) from ZeBu; you can take this into parallelized expansion, or you can use a high-performance interactive/selective expansion to pick out just the signals you want to check. Synopsys have also added a native ZeBu database to Verdi to speed up load times. Together they say this decreases waveform expansion and load times by 10X.

This is a quick overview of how to drive efficient debug for emulation on big designs with big use-cases. You can watch the webinar HERE.

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Webinar: Addressing Multiphysics Challenges in 7nm FinFET Designs

Webinar: Addressing Multiphysics Challenges in 7nm FinFET Designs
by Daniel Nenni on 03-12-2019 at 7:00 am
Categories: Ansys, Inc., EDA, FinFET

EDA is big on growth through acquisition, being acquired many times throughout my career I know this by experience. In fact, we have a wiki that tracks EDA Mergers and Acquisitions and it is the most viewed wiki on SemiWiki.com with 101,918 views thus far.

In March of 2017 ANSYS acquired CLK Design Automation which did timing variation analysis and FX for transistor model and simulation. At the time I worked for Solido Design who had some overlap with CLK and we actually looked at acquiring them before ANSYS did. The jewel in the crown of CLK was the technologists and one of those jewels is Dr. Joao Geada, absolutely.

Bio:Dr. Joao Geada is a chief technologist at ANSYS, with over 20 years of EDA experience. He leads the development of the semiconductor business unit’s FX timing and timing variation products. He is the author of numerous papers and patents around static timing analysis and statistical timing. Before ANSYS, Dr. Geada was CTO and co-founder of CLK Design Automation and one of the lead architects in the verification and simulation group at Synopsys. Before Synopsys, Dr. Geada was a senior researcher at Cadence Design Systems and started his career at the IBM TJ Watson Research Center. Dr. Geada holds a Ph.D. and bachelor’s degree in engineering from the University of Newcastle on Tyne (UK).

Dr. Geada is the speaker for the upcoming webinar Addressing Multiphysics Challenges in 7nm FinFET Designs.Even if you can’t make the live webinar sign up and you will be notified when the replay is up:

Date: March 28, 2019
Time:9 a.m. PST
Presenter: Dr. Joao Geada, Chief Technologist, ANSYS

Webinar Link:http://bit.ly/2C8pF3B

Abstract:
Variability has become the new enemy in 7nm FinFET designs. You can’t fix what you can’t find, and variability takes many forms. For instance, there is variability in process due to smaller geometries, variability in voltage drop due to varying workloads and variability in temperature across the chip due to increased self-heating and joule heating effects. All directly impact silicon performance. Increased cross-coupling of various multiphysics effects such as timing, power and thermal in 7nm designs poses significant challenges for design closure. Power grid design and the profound impact of grid weakness issues on timing-critical paths have become limiting factors for achieving the desired performance and area targets. Power grids consume a significant amount of metallization resources, and with routability becoming a big constraint at advanced nodes, power and timing closure have become a designer’s nightmare.

Traditional margin-based methodologies that have served well in the past are becoming ineffective. These methodologies helped in confining the problem space by decoupling design methodologies to manage complexity and limitations in electronic design automation (EDA) tools that are not architected to solve multiphysics challenges. At 7nm process nodes, however, these siloed methodologies are increasingly failing to achieve the highest performance in silicon. Margins work well only as long as the results are predictable. With the margin-based approach, increased variability makes it hard to predict true silicon behavior and impacts both time-to- result (TTR) and time-to-market (TTM) goals in complex design projects.

Attend this webinar to learn how ANSYS multiphysics simulations can be leveraged for better understanding the true limits of built-in margins and accurately predicting post-silicon behavior. Multiphysics simulations will enable you to achieve the target maximum frequency on silicon, while drastically improving the functional yield of your chips.

About ANSYS, Inc.
If you’ve ever seen a rocket launch, flown on an airplane, driven a car, used a computer, touched a mobile device, crossed a bridge, or put on wearable technology, chances are you’ve used a product where ANSYS software played a critical role in its creation. ANSYS is the global leader in Pervasive Engineering Simulation. We help the world’s most innovative companies deliver radically better products to their customers. By offering the best and broadest portfolio of engineering simulation software, we help them solve the most complex design challenges and create products limited only by imagination. Founded in 1970, ANSYS employs thousands of professionals, many of whom are expert M.S. and Ph.D.-level engineers in finite element analysis, computational fluid dynamics, electronics, semiconductors, embedded software and design optimization. Headquartered south of Pittsburgh, Pennsylvania, U.S.A., ANSYS has more than 75 strategic sales locations throughout the world with a network of channel partners in 40+ countries. Visit www.ansys.comfor more information.

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Accelerating SOC Development for Automobile Applications

Accelerating SOC Development for Automobile Applications
by Tom Simon on 03-11-2019 at 12:00 pm
Categories: Automotive, IP, Synopsys

No area of electronics is moving faster than automotive semiconductors. Everyone has been talking about the increasing electronics content of automobiles for decades. With Advanced Driver Assistance System (ADAS) and autonomous driving becoming a reality the pace has picked up even more. These new designs combine just about every single advanced subsystem used in SoC designs. Prior to the giant leap in mobile device technology, people talked about how there was a ‘convergence’ coming that would integrate communications, networking, graphics, processing, etc. That did indeed happen with the result being the current generation of cell phones.However, a new convergence is coming.

With ADAS and autonomous driving, we are essentially talking about putting advanced supercomputing along with state of the art sensor fusion, multiple modes of wired and wireless networking, high-speed memory, and advanced algorithms into each car. The rigid power, security, and reliability constraints on these new systems make this a more daunting task. Exciting new companies like FABU Technology have come along to address the growing market for AI SoCs with innovative designs targeted at ADAS and autonomous driving.

FABU has set out to rapidly build SoCs for ADAS and autonomous driving that can collect sensor data from gyro, accelerometer, compass, vision, lidar and radar systems, then combine them with maps, real time traffic and road condition data to create an accurate view of the vehicle’s environment. Surrounding vehicles, traffic signs, and pedestrians must be identified. Additionally, the ADAS and autonomous driving systems need to monitor the driver to detect driver attentiveness, distraction or drowsiness.

The market is moving too fast for a company like FABU to set out to build the required automotive IP from scratch. At the same time much of the IP needed is specialized and has be built to automotive standards. These standards include ISO 26262 and AEC-Q100. In order for them to focus on their core competency, FABU chose to license a broad swath of the necessary IP from Synopsys. Their automotive-grade DesignWare IP offerings are ideally suited to FABU’s needs.Going this route allows FABU to focus on where they add value – implementing highly optimized algorithms – while leveraging IP that meets their functional needs as well as all automotive reliability and security requirements.

I had a chance to speak recently with Ron DiGiuseppe, senior marketing manager for automotive IP products at Synopsys, about FABU’s choice for IP. They worked closely with FABU to help them select the optimal interface, security, processors, and foundation IP solutions. Interface IP is being used to collect data from sensors, such as MIPI for image and video.

FABU will be using the Synopsys Safety Island for its ARC processors with dual lockstep cores, which have an independent safety monitor to check for faults and failures. In the event of a safety exception there is an escalation to the host processor where it can be independently processed.

Ron also talked about the need for security. The last thing you want is security intrusions. Synopsys IP offers hardware Root of Trust with encryption and a trusted execution environment (TEE) to prevent tampering and other malicious activities.

By licensing the broad portfolio of IP from Synopsys, FABU will benefit from consistency in the deliverables, especially with respect to documentation for ISO 26262 and IP integration. Ron pointed out that Synopsys will work with FABU to ensure selection of the ideal process node to meet their PPA and safety requirements. Synopsys has built relationships with foundries for automotive processes as part of their commitment to this market. FABU can use the licensed IP as a foundation for creating SoCs that offer breakthrough functionality and performance. The announcement contains detailed information on each of the categories of IP that they licensed and information about how each of them meets the requirements for automotive applications.

Synopsys automotive-grade DesignWare IP comes with documentation for ISO 26262 compliance and their automotive IP is ASIL B or D Ready. For reliability, Synopsys works with foundries to ensure AEC-Q100 compliance. This involves producing GDS layout that meets the more stringent automotive reliability including design rules for Grade 1 and 2 temperature. Another area where Synopsys adds value for the automotive market is with their test and repair tools, which further improve quality and reliability.