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Let’s Pass the Hot Cars Act of 2019

Let’s Pass the Hot Cars Act of 2019
by Roger C. Lanctot on 10-27-2019 at 10:00 am
Categories: Automotive
1 Comment

It’s happened again. The 42nd fatality of 2019 in the U.S. from a child being left behind in a hot car has occurred – this time, in New Mexico. While horrific and staggering, the total number of fatalities due to children being left in overheated cars for 2019 is still less than the 54 fatalities suffered in 2018.

According to Kidsandcars.org, a child dies after being left behind in a car every nine days in the U.S. The situation is reminiscent of 2007 when the U.S. Congress signed the Cameron Gulbransen Kids Transportation Safety Act into law requiring the National Highway Traffic Safety Administration to set rear visibility standards by 2011. At the time, 200 people were killed and 14,000 injured annually in backover incidents.

As of 2018, and after extensive testing and research, all cars sold in the U.S. were required to come with a backup camera system. In the same spirit, Kidsandcars.org has been promoting legislation – widely supported by dozens of safety advocates and organizations – to require a rearseat passenger detection system.

The core of the proposed legislation states: ” Not later than 2 years after the date of the enactment of the Hot Cars Act of 2019, the Secretary (of Transportation) shall issue a final rule requiring all new passenger motor vehicles with a gross vehicle weight of 10,000 pounds or less to be equipped with a system to detect the presence of an occupant in a rear designated seating position after the vehicle engine or motor is deactivated and engage a warning. In developing the rule required under this subsection, the Secretary shall consider requiring systems that also detect the presence of any occupant unable to independently exit the vehicle as well as detect the presence of a child who has entered an unoccupied vehicle independently.”

The act would have the added benefit of protecting children and disabled adults as well as pets, which also suffer when forgotten in overheated vehicles.

Safety advocates can be forgiven for being disappointed in the news that arrived last week of a voluntary agreement between safety regulators and the auto industry for the introduction of visual and audible rearseat reminder alerts – after the vehicle is turned off. The agreement provided for fitment of such an alert in all new cars sold in the U.S. beginning in the 2025 model year.

This voluntary agreement is largely a reflection of the need to short circuit the normal broken and bureaucratic NHTSA regulatory process which can extend for years – 11, to be exact, in the case of the Backup Camera mandate. It’s a nice good faith effort, but it shows the U.S. auto industry once again out of step with the rest of the global industry.

The Federal government in the U.S. is currently seeking to undermine emissions and fuel efficiency standards, while governments elsewhere in the world are setting deadlines for the end of the sale and use of internal combustion engine driven vehicles within decades. European regulators are requiring driver monitoring systems, while U.S. regulators are nudging the industry toward the introduction of rearseat alerts.

The voluntary approach to industry-wide safety system adoption in the U.S. was first instituted three years ago for automatic emergency braking (AEB). In 2016, 20 auto makers agreed with NHTSA and the Insurance Institute for Highway Safety to install AEB on “nearly all US vehicles” by 2022.  Now, 20 auto makers have agreed to do the same for Child Presence Detection by 2025.

If NHTSA were to have pursued a mandate for AEB, the process would still be underway with heated debates over different technical solutions. Voluntary adoption of AEB has saved time and money and, presumably and eventually, lives.

Meanwhile, Europe’s NCAP (New Car Assessment Program) is requiring the introduction of driver monitoring systems (to mitigate fatalities and injuries resulting from drowsy or inattentive drivers) by 2022, mandating the technology for all vehicles by 2024. Starting next year, Euro NCAP’s coveted and coercive five-star safety rating will only be available to cars equipped with driver monitoring systems. Of course, the precise nature of these systems is yet to be determined.

Critics of the voluntary implementation of rearseat passenger detection technology in the U.S. suggest that the proposed solution is insufficient to correct the problem. Since the program is voluntary it is likely that different auto makers will take different approaches with different levels of efficacy.

The bigger issue, of course, is the struggle that NHTSA faces in pushing more active safety systems, such as automatic emergency braking, in the interest of mitigating the escalation in highway fatalities. The challenge of ending the scourge of heat-stroke deaths among left behind children in cars may serve as sufficient motivation to call for camera-based in-vehicle monitoring systems capable not only of detecting children left behind in rearseats, but also minding an inattentive driver.

Approximately 4,000 fatalities and 400,000 injuries are attributed to driver distraction every year in the U.S. Camera-based driver monitoring systems will be capable of simultaneously detecting the presence of children, pets, and disabled adults left behind in rearseats while also monitoring driver behavior.

A little camera and a little code could go a long way to saving lives and making driving safer for all. General Motors is actually in the vanguard of introducing camera-based driver monitoring technology – with its Super Cruise enhanced cruise control system on select Cadillacs. The Super Cruise system will allow Cadillac drivers to take their hands off the steering wheel while driving as long as the car is on a Super Cruise-compatible highway and the driver is paying attention to the road.

In essence, it may be time to mainstream driver monitoring systems. The only question remaining is will it take a mandate, or just good sense?

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TSMC Update Q3 2019 Absolutely!

TSMC Update Q3 2019 Absolutely!
by Daniel Nenni on 10-25-2019 at 6:00 am
Categories: Events, Foundries, TSMC
4 Comments

This will be a combination of the recent TSMC quarterly report, a look back at Cliff Hou’s keynote at the most recent TSMC conference, and conversations on SemiWiki.com. There has been a lot of press on this but of course the most important points are being missed. Semiconductors are complicated and getting more so, absolutely.

The big news out of the conference call was the increase in TSMC Capex from $12.5B to an even $15B which will be repeated in 2020 ($15B) and grow in 2021 due to increasing demand. Remember, TSMC closely partners with customers and builds capacity based on demand (wafer agreements) and not imagined demand like IDMS (Intel and Samsung).  On the technology side lets look at the opening statement from the transcript:

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO Now I will talk about our N5 and N3 status. Our N5 technology has already entered risk production with good yield. The N5 will adopt the EUV extensively and is well on track for volume production in the first half of next year. With 80%, 8-0, logic density gain and about a 20% speed gain compared with the 7-nanometer, our N5 technology is true full node stride from our N7. We believe it will be the foundry industry’s most advanced solution with the best density, performance and power until our 3-nanometer arrives. With N5, we are further expanding our customer product portfolio and increasing our addressable market. The initial ramp will be driven by both mobile and HPC applications. We are confident that 5-nanometer will have a strong ramp and be a large and long-lasting node for TSMC.

Daniel Nenni – Founder – SemiWiki.com LLC:. 5N may be considered a full node from 7N but not 6N (with an 18% density advantage over N7). In my opinion the 6nm node will be a VERY long lasting node and while 6N revenues will be lumped into 7N and 7N+, 6N revenue will rule all, my opinion.

5N and 3N will also share the same fabs as did 10N and 7N which will again speed HVM ramp and reduce development costs. It is the TSMC recipe to foundry success, absolutely.

According to a conversation on SemiWiki, N5 is said to be 30nm M2P and 50nm CPP with 6 tracks and 173MTx/mm2. This works out to ~1.8x denser than N7 which is what TSMC has said. Scott Jones is pretty sure M2P is ~ 30nm and 50nm for CPP which is what is needed to get the 1.8x density improvement they have discussed.

N5P was not mentioned but from what was discussed on SemiWiki N5P is the same design rules, just more strain, a performance enhancement. Apple requires a new process every year so this is it. N5P will be out in 2021 for the Apple iProduct refresh. I would expect more optimizations will be announced next year so you may see a density improvement based on better EUV or something like that.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: Our N7 process is the industry’s first commercially available EUV lithography technology. N7+ provide 15% to 20% higher density with improved power consumption when compared to N7. That is already in high volume production with yield similar to N7. We expect the strong demand for N7+ continue into next year and are increasing Capex to meet this demand for multiple customers.

Now N6. Our N6 provide a clear migration path for the second-wave N7 product as its design rules are 100% compatible with N7 while providing 18% logic density gain with performance-to-cost advantage. The N6 uses one more EUV layer than N7+. N6 risk production is scheduled to begin in first quarter next year with volume production starting before the end of 2020. We reaffirm 7-nanometer will contribute more than 25% of our wafer revenue in 2019 and we expect even higher percentage in 2020 due to worldwide development of 5G, accelerated demand from HPC, mobile and other application continue to grow.

Daniel Nenni – Founder – SemiWiki.com LLC: Remember, 7N/6N is 28N déjà vu all over again so there will be plenty of 6N capacity moving forward once Apple and the other mobile giants move to 5N. The big difference between 6N and 28N is that there will be no cheap knock-off processes from UMC and SMIC, not even close.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO Now I will talk about the N3. We are working with customers on N3 and the technology development progress is going well. Our N3 will be another full node from our N5 with PPA gain similar to the gain from N7 to N5. We expect our 3-nanometer technology will be the most advanced foundry technology in both PPA and transistor technology when it is introduced.

Daniel Nenni – Founder – SemiWiki.com LLC: TSMC N3 will again use FinFETs unlike Samsung who will use GAA which highlights the real difference between Samsung and TSMC. TSMC is focused on manufacturability versus bleeding edge technology. TSMC does not really have a choice here since they have the mobile giants (Apple, Huawei, etc…) pushing them for a new process node every year that can yield at a very high rate right out of the box. GAA will be 2nm for TSMC.

Packaging was also a focus of the call. We covered packaging and design enablement here:

A Future Vision for 3D Heterogeneous Packaging

A Review of TSMC’s OIP Ecosystem

Now for the relevant Q&A:

Gokul Hariharan – JP Morgan Chase & Co, Research Division – Head of Taiwan Equity Research and Senior Tech Analyst: So first of all, if we look at the history, whenever TSMC has had a step-up in CapEx, that is typically accompanied by a step-up in growth as well. So just wanted to kind of narrow down a little bit on the 5% to 10% growth, which is still kind of — the kind of growth that we were expecting when we were spending TWD 10 billion to TWD 11 billion. So could you give a little bit more details or maybe narrow down the forecast a little bit more for us? Because if we say a TWD 14 billion to TWD 15 billion range of CapEx, that’s closer to the high 30s or 40% capital intensity, higher than our previous range.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: Gokul, let me answer the question carefully. Let’s say that TSMC always build capacity, working closely with customer and to meet their demand. That’s our number one, okay? We discuss with the customer on their demand, we make our judgment also. Now we are increasing the CapEx quite a lot, no doubt about it. But then, that’s due to some of the reasons I can foresee for the future. First, the 5G’s ramp-up is much faster than 4G as we expected. Second, TSMC actually is expanding our customer portfolio, and in the same times, we’re also expanding our product portfolio. And so put all the factors together, we have a good reason that we increase our CapEx this year and probably next year.

Daniel Nenni – Founder – SemiWiki.com LLC: I was hoping packaging would come up in the Q&A. From the very beginning TSMC’s packaging efforts were looked at as a low margin business but it is also a VERY sticky business, much stickier than the wafer business. The mobile giants depend on packaging and they now “depend” on TSMC for packaging, absolutely.

Charlie Chan – Morgan Stanley, Research Division – Technology Analyst: Okay. And my next question is about the advanced packaging. I remember in the previous quarters, you commented advanced packaging should outgrow the front-end business. So first of all, is this remains the same trend? And also how about the potential margin dilution from the packaging business?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: The forecast on the advanced packaging business, the growth is — the growth rate is still faster than silicon growth rate. The wafer’s revenues growth rate stays the same, okay? Still that statement is still valid. The gross margin, that’s another consideration. The gross margin of the back-end business actually is lower today, still lower than the wafer margin. But we look at it whether it’s a good business to go or not on 2 factors. One, we really want to support our customer to improve their system performance. So we have to do it because of TSMC is the only one company right now who can support customers’ advanced packaging. Second actually is the CapEx intensity on the back end, and that’s advanced packaging business, is smaller. And so the asset turnover is better. So put all in all together, we still think it’s a very good business to pursue.

Daniel Nenni – Founder – SemiWiki.com LLC: As expected, the China question. TSMC’s China strategy started with Morris Chang many years ago and is nothing short of brilliant. Morris may or may not have seen the US-China trade riff coming but he positioned TSMC perfectly. TSMC has more than 400 active customers and more than 100 of those are now in China. In Q3 2019 China accounted for 20% of TSMC revenue, up from 15% last year. North America is -2% to 60%, EMEA is -1% to 6%, Asia Pacific is –1% to 9%, and Japan is -1% to 5%. I expect this trend to accelerate as the US and China continue to play economic politics.

Brett Simpson – Arete Research Services LLP – Senior Analyst: I had a question really on China. I guess in the last couple of years, we’ve seen the business double with Chinese customers. I guess at the moment, it’s pretty clear you’re going through a very healthy inflection point in the Chinese customers at the moment. So can you talk about how you see this part of the business evolving over the next 1 or 2 years? And then I guess from a planning perspective, are you concerned that the rise of your China business comes at the sacrifice of other customers, particularly U.S. companies?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: Well, we did see the strong course from China because that’s a very big market, especially in the semiconductor area. And we are happy to see that growth, and TSMC is offering the most leading-edge technology to support our customer in China. And so to be exact, we are going to grow with the China market. At the expense of other customer, the answer is no because we support all the customer with all our strength and our capacity.

Daniel Nenni – Founder – SemiWiki.com LLC: Interesting EUV question. I don’t remember TSMC publicly saying they made their own pellicle but of course we all knew. Yet another TSMC differentiation.

Roland Shu – Citigroup Inc, Research Division – Director and Head of Regional Semiconductor Research: Okay. And the second question is you announced that your EUV tools have been reached potentially maturity, but how about for the infrastructure? It means that for other component like photoresist, pellicle, photomask or even for this inspection tools, chemical and materials. So yes, we have — going to have a very fast ramp on 5-nanometer because of very strong demand from a customer, but are there any gating items for this EUV infrastructure will be potentially a risk?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: So far we do not see any gating item. All the infrastructure, actually TSMC, we are prepared. We have a — we produce our own pellicle. We have a large number of masking capacity and everything. So even photoresist, those kind of thing, we have been taking into account. So we are ready for the — actually, we are in a high-volume production for the EUV lithography technology. For next year, you have big — even higher volume, and I can assure you that we are all prepared.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: Okay. In TSMC, EUV lithography technology is now in the production stage. But are we happy with that? Not yet. We are still improving availability. We have output power of 250 watts, as we expected. Now we can operate the tool with 250 watts consistently. However, there’s still something that we need to improve so that we can improve the throughput, we can improve the availability so you can reduce the cost, continue to improve.

Daniel Nenni – Founder – SemiWiki.com LLC: And I’ll finish this blog with the lighter side of the Q&A. Remember this is live in front of an audience in Taipei and C.C. says this stuff with a straight face. It really is fun to watch:

Roland Shu – Citigroup Inc, Research Division – Director and Head of Regional Semiconductor Research: Okay. I think just a follow-up for — I know you don’t comment on the ASP, but for the same amount of the wafer shipment on N7+, is this going to contribute more revenue upside to TSMC?

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: You just mentioned we don’t.

Roland Shu – Citigroup Inc, Research Division – Director and Head of Regional Semiconductor Research: No, I talk about revenue. I don’t talk about ASP.

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: That’s the same thing.

Bruce Lu – Goldman Sachs Group Inc., Research Division – Research Analyst: That’s why I wanted you to give us some hint, right? We cannot just tell my investors that we have to trust TSMC. Even though I say that all the time but…

C.C. Wei – Taiwan Semiconductor Manufacturing Company Limited – Vice Chairman & CEO: You can trust TSMC. No doubt about it.

Daniel Nenni – Founder – SemiWiki.com LLC: Absolutely!

Reference: https://www.tsmc.com/uploadfile/ir/quarterly/2019/3d36C/E/TSMC%203Q19%20transcript.pdf

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IP-XACT helps you produce exactly what you need in SoC deliverables

IP-XACT helps you produce exactly what you need in SoC deliverables
by Tom Simon on 10-24-2019 at 10:00 am
Categories: EDA, Magillem

If you have ever watched an experienced glass blower, your first thought is that they make it look so easy. I have had the opportunity to blow glass, and I can tell you that it is a constant struggle against temperature, time and muscles to get the glass to do anything like what you want. This is akin to what is required to take the elements of an IC design and provide each of the deliverables to various stakeholders. When it is done right, it can look effortless and straightforward; when done wrong it leads to chaos and confusion. In glass blowing there is no substitute for practice and experience – I know this firsthand. Fortunately for IC design teams there are tools, like Magillem’s IP-XACT solutions that can make the process relatively straightforward.

Magillem offers a suite of IP-XACT tools, based on the IEEE 1685 standard, that help create deliverables for the various consumers of the design data for an SOC. Who are these consumers? They might be internal teams that have to work on the design at various stages, such as simulation and verification teams. Alternatively, they might be other groups within a company that are using the design for their own projects. Lastly, they can be external consumers of the design in the form of hard or soft IP. Hard IP can even be targeted for delivery for specific technologies.

There is the need to hand off simulation models, RTL (clear and encrypted), netlists (hierarchical or flat) and even hard macros. The data provided might only need to be for a subunit of the hierarchy, or for the entire design. IP-XACT makes it easy to associate specific file sets with different views of the design. Then those files can be turned into deliverables. IP-XACT leaves all design data in its native format, which means that it does not interfere with design tools in any way.

Magillem’s IP-XACT tools allow for centralization of all the design files and related information. Production of each deliverable can be automated to provide precisely what is required for each of the deliverables. They also provide checking mechanisms that help assure the deliverables meet quality standards.

IP-XACT can also help organize and release collateral information such as test benches, documentation and verification related files. Magillem will be presenting at DVcon Europe shortly on how IP-XACT can help with highly configurable IPs. The presentation will also delve into how IP-XACT can help with restructuring IP to improve implementation. Also, they will talk about how IP-XACT can help address the needs of ISO 26262 in the design and delivery process.

When I was blowing glass, I remember looking into the blazing hot furnace holding the molten glass and envisioning the next piece I would make. My ability to control the glass was the make-or-break factor determining my success. It is not unlike having SoC design data and needing to pull out the relevant parts for each deliverable. The skill and precision applied to the task determines the end result. Magillem IP-XACT tools can play a crucial role in effectively developing and then utilizing the design data for an SoC. Further information about Magillem’s comprehensive IP-XACT based solutions can be found on their website.

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Accelerating Functional Safety Verification

Accelerating Functional Safety Verification
by Bernard Murphy on 10-24-2019 at 6:00 am
Categories: Automotive, EDA, Synopsys

FuSa Verification

Verifying a design for functional safety requirements for an IP or SoC per ISO 26262 is a complex process that can’t be encapsulated in one tool. Process complexities depend on whether the Tier1 or OEM is targeting safety-levels ASIL-A , B, C or D, where ASIL-D applies to anything truly safety-critical such as airbag controls or automatic braking and steering. A concern for any IP maker or SoC integrator is the implications of safety element out of context (SEooC) testing which may impose additional requirements from higher levels in the integration-chain. You also need to know that tools used in your flow meet the appropriate confidence levels (TCL) to align with the target ASIL level.

Figure 1: Synopsys Unified Functional Safety Verification Solution

Demonstrating and documenting compliance to the next level of integrators is what ISO 26262 compliance is all about and why you need safety managers, processes, culture and systematic methods to generate supporting documentation for your integrator consumers. That documentation includes FMEA reports to determine and justify where failures might occur so that safety mechanisms can be planned to mitigate those failures, and FMEDA reports to demonstrate that those mechanisms deliver as expected in simulated modeling of failures. Integrators also want to see tool safety manuals and certifications. All of this is needed in support of audits each member of the chain will run on their suppliers and that their consumers will run on them.

Anyone building IP or SoCs for modern automotive markets must invest significant resources and infrastructure to meet these needs. One way Synopsys aims to simplify and accelerate the task is in offering a unified functional safety verification solution. This includes more than I had expected, starting with a unified umbrella for fault campaign management. The tool that supports this step is the VC Functional Safety Manager which triggered part of my surprise in that it starts with FMEA analysis. That step has been historically left to design teams to handle since the questions it asks hovers on the edge between design know-how/intent and the design structure. You obviously can’t automate all of this away but it can be simplified through ability to import baseline architectural info from spreadsheets, ability to specify failure modes and safety mechanisms, and maps all of this to a detailed FMEDA.

The manager provides preliminary estimates of coverage through estimates of safety mechanism versus fault mode coverage and initial ISO 26262 metrics, so you can guide design improvements (for example adding or changing safety mechanisms). Design details for these estimates are extracted from existing RTL/netlist data for the design.

The manager will also execute the fault campaign, generating tool setup, running the fault sims and updating the ISO 26262 metrics and iterating as needed. Finally the manager will export the FMEA and FMEDA documentation, per component and for the SoC as appropriate, in a form that can be handed off to assessors and consumers at the next level of integration.

A lot of tools run under the manager. These include TestMAX FuSa (functional safety), a fast-static analysis (interestingly based on SpyGlass) to calculate early single point fault metrics and provide information on how to improve these grades. For analog circuitry, TestMAX Custom Fault will analyze analog/AMS designs for functional safety and coverage. For digital circuitry, the Z01X fault simulator runs concurrent fault sims in support of the fault campaign and the VC Formal app complements this by classifying faults according to controllability and observability reducing simulation cycles (why check a fault if you can’t observe the consequences of that fault?). ZeBu emulation enables longer run-time analyses. Also Certitude can be used to test process robustness against systematic fault, a nice way to add certainty to the completes of the analysis.

Amid all the significant overhead in instrumenting and demonstrating compliance, especially to expectations for autonomous and semi-autonomous vehicles (ASIL-D), I can definitely see value in this level of integration, automation and pushbutton generation of audit deliverables. Integrators need less things to worry about in their own compliance activities. You can learn more about the Synopsys safety verification flow HERE.

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WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®
by Daniel Nenni on 10-23-2019 at 10:00 am
Categories: Cliosoft, EDA, Events

In September, ClioSoft gave a SemiWiki webinar titled, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. I was happy to be the moderator of this webinar, having had the chance to work with ClioSoft’s team over many years. The webinar was informative while also being very time efficient. I think it is important for most design managers, analog designers, and EDA system architects to watch and well worth the time for most layout engineers as well.

I think all in the audience will understand the need for reuse. But we don’t always consider all the ways that reuse can be applied. In its most basic form, it simply means to reuse parts of a design that were already created in a different design project. It is a straightforward concept when we think about major functional blocks or subsystems. The larger the function that is reused, the more likely it may need to be modified for use in a new design. The fact that some modification may be needed is not necessarily bad; it is just a bit of additional effort. Modifying the previous IP may be much more efficient than creating a new solution from scratch.

It is also not simply major functional blocks that can be reused. You may also need to tune analog functions for a given process. Reusable analog IP is highly valued.  For example, a PLL design for use in on design may be easily reused in another design on the same process. While it cannot be directly reused in another process, it may be fine with some small modifications. This is especially valuable if the prior design is in silicon, and real performance data now exists for the block. Of course, the reuse of IP should also extend to all of your foundation IP – standard cell, IO cells, memory instances, PLLs, etc.

Saving all your IP is important. However, you need to be able to find the IP when you need it and also have the information you need to utilize that IP. ClioSoft’s designHUB® was built to make it easier to store, locate, and apply your valuable IP. designHUB® first started shipping in May of 2017 has been successfully deployed in many companies. This webinar goes into more detail on how you can use designHUB® in your design environment.

The primary presenter in the webinar is Karim Khalfan, ClioSoft’s Vice President of the Application Engineering. Karim has led the deployment of ClioSoft’s SOS7 design data and IP management into ClioSoft’s large customer base. He has also written several articles and white papers related to SoC design data management. Karim has a BSCS degree from the University of Texas and holds a patent on defining a universal data management adapter to be used for integration with any EDA tool. As you will see in the webinar, he is can clearly explain this technology.

To access the replay of this webinar, go to this page and click on “View recording.”  This webinar is one of several in this year’s SemiWiki Webinar Series. A list of upcoming webinars, as well as other available replays, can be found in the left column on the SemiWiki homepage.

 

Also Read

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

For EDA Users: The Cloud Should Not Be Just a Compute Farm

IP Provider Vidatronic Embraces the ClioSoft Design Management Platform

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LRCX – A recovery without memory? Korea share gain? TSMC bonus?- all upside

LRCX – A recovery without memory? Korea share gain? TSMC bonus?- all upside
by Robert Maire on 10-23-2019 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services

LAM will likely bounce on Korea gains & TSMC
Memory still sucks but TSMC is hot!
Korea upside from share gains?
Japan/Korea – The “Beer Barometer”

Looks like a good Q3….
We think when Lam reports their Q3 this wednesday it will likely be a positive catalyst for the stock as we think the report will be better than expected and guided and guidance for Q4 is likely to also be better than expected.

We are not suggesting that the cycle is over and we are “off to the races” but rather that there are some near term drivers that will cause a bounce off the bottom that we have been bouncing along on.

We would caution investors to not get overly excited as memory is still in the dumps and associated spending on memory is still weak at best.  Memory spend is not likely to recover any time soon given excess capacity and the current situation.

Logic/Foundry is Hot
Logic/foundry, however is hot, very hot, as we have heard from TSMC, which bumped up its capex plans by a whole lot and looks like they will have a very big “hockeystick” of spend at the end of the year. While a real, full blown recovery would be both memory and logic recovering at the same time, we will have to be happy with the industry bouncing nicely on a primarily logic lead recovery.

As we have repeated many times, we have been expecting a logic led recovery as memory remains over supplied as many machines remained idled.  Those machines have to come back on line first before the industry will even consider buying new memory tools…likely a long ways off.

Korea share gains at the expense of Japan
For several months we have talked about share gains we expect to see of US companies, like LRCX & AMAT versus Japanese companies like TEL & Hitachi in Korea due to the ongoing trade dispute between Korea and Japan which is far from over.

The dispute is far worse than the US/China trade dispute as it has pushed to the surface, decades long simmering animosity over past cultural/political issues.

Korea, its people, its government and its industry have all reacted very negatively, in unison, to Japan and its products.  We think this will mean substantial losses for TEL and Hitachi and gains for Applied & Lam as Korea seeks to replace all things Japanese with anything else.

Semes, a semiconductor equipment arm of Samsung is likely the biggest winner over the long run but in the near term its better to buy US equipment than Japanese.

We would expect to hear that Lam is doing better in Korea…wether they admit to or talk about share gains at the expense of the Japanese is another thing.

The “Beer Barometer”
In case you think I am joking or making this up take a look at Japanese beer sales in Korea.  Ashai beer from Japan has long been a dominant force in Korea with very large market share.

In August, Japanese beer sales in Korea were down 95% (yes you read that right) due to the dispute and a public boycott of Japanese beer.

While you may then think that this has nothing to do with semiconductor equipment, we have heard that the Koreans have asked that even US made semiconductor equipment, in some cases, not have Japanese manufactured sub components, so as to avoid anything related to Japan being imported into Korea

Japanese Beer Sales in Korea Link

Germany is benefiting at the expense of Japanese car makers as Korean purchases of Japanese cars is down 60%

Germany share Gains versus Japan in Korea

We think we will see similar, maybe not as bad, news as it relates to Japanese versus US made semiconductor equipment.

Collateral Benefit
Aside from what we think will be good news for Lam, we would also expect US suppliers to the industry to benefit. Two of our favorite suppliers to the industry that will definitely benefit from the upside we expect will be MKS Instruments (MKSI) and Ichor (ICHR).

We think there may even be more upside in these suppliers as Lam, Applied, ASML and KLAC have all run up in anticipation of some sort of a recovery but the sub suppliers and smaller market cap companies have lagged this run up.

This is how it works in all of the many past cycles we have been through…..the large cap names recover first followed a quarter or two later by the smaller cap names and sub suppliers to the industry.

The Stocks
We have no problem going out and buying in front of the quarter as we think there is an opportunity for a nice near term uptick, some of which we have seen a preview of.  In general, we think some of the smaller cap names have more upside as investors start looking around for other names not wanting to pay up for the large caps which have already had a strong run.

We also would not have any qualms about taking some money off the table after some strong quarterly news and gains as we may not get another catalyst after the quarterly reporting is done.  We also do run a small risk that after spending strongly for a couple of quarters, TSMC could slow down again before memory ever wakes up.  The odds of Korea and Japan kissing and making up is much lower and likely to be a longer term issue.  We still have the US/China trade dagger over the industries head but the administration seems to be pre-occupied doing other odd things and is less focused on trade…at least for a while.

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Statistically speaking you probably care about On-chip Variation

Statistically speaking you probably care about On-chip Variation
by admin on 10-22-2019 at 10:00 am
Categories: EDA, Events

There are some metaphorical similarities between reaching timing signoff and driving a car to your destination. Most of us get in the car, turn the key and push the gas pedal to make it go. While we might have a cursory understanding of what makes it go, there are actually a lot of “moving part” under the hood in each instance. For most car drivers it is not an issue if they don’t really understand the workings of their automobile. However, in the case of timing signoff, it’s pretty important that designers and engineering managers understand how things work.

Silvaco is in an interesting position when it comes to understanding timing signoff. They develop tools across the spectrum, from TCAD to SPICE, library characterization and timing tools. This is why their recent webinar about “On-Chip Variation and the Sign-off Timing Flow: An Industry Perspective” was so interesting. With larger designs, smaller process nodes and higher volumes, timing signoff has become much more challenging over the years. On-chip variation has become a huge factor in determining silicon success and yield.

The webinar covered the various factors that lead to variation and how timing signoff methodologies have had to adapt to consider these new factors. When signoff methodology changes, the models that are used to drive the tools also need to change, to offer the information needed by the tools that use them. As a result, library characterization has been an area that has seen active development and significant advances.

The webinar presenter, Bernardo Culau, Director of Library Characterization at Silvaco, did an excellent job of reviewing how the needs and methods for timing signoff have evolved, from the early days of OCV modeling to the latest statistical methods. He provided an concise overview of the sources of variation and how each generation of sign off tools has progressed to reduce pessimism and increase efficiency to keep up with growing complexity.

Variation is caused by just about anything that can fluctuate during chip fabrication and later on during operation. On-chip variation specifically addresses difference in fabrication parameters, and operational temperature and voltage within a given die. This includes such things as channel width, dopant fluctuations, dishing, lithography issues, etc.

Bernardo untangled the alphabet soup of library formats and techniques. Among there were: OCV, SBOCV, AOCV, POCV and finally LVF. The variation modeling techniques needed vary with process node. Older nodes such as 90nm can get by with simpler models. By the time we get to 7nm, only the most advanced statistical methods can be relied on.

An important point he touched on was that statistical methods need to move from relying on Gaussian distributions and move to Moment Based LVF. More information needs to be included in the model files for the true distribution to be properly represented.

Bernardo concluded with an overview of the suite of Silvaco tools for library characterization. Their Viola tool uses parallel processing to complete cell characterization and is compatible with all the leading SPICE simulators, including Silvaco’s own SmartSpice. Cello is used for library migration, and they also offer a Liberty Library Analyzer. Their Jivaro tool can help improve efficiency by performing parasitic reduction with minimal impact on accuracy.  VarMan is their flagship solution for exploring the yield impacts on a design caused by variation.

If you want to improve your understanding of what is happening under the hood in timing signoff, this webinar provides a wealth of information. I for one like to know about the specifics, because the additional knowledge could make the difference between being stranded on the road or safely getting to your destination. The full replay of this webinar can be found through the Silvaco website.

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Safety and Platform-Based Design

Safety and Platform-Based Design
by Bernard Murphy on 10-22-2019 at 5:00 am
Categories: Arm, Arteris, Automotive, IP
1 Comment

Safety infrastructure in platform design

I was at Arm TechCon as usual this year and one of the first panels I covered was close to the kickoff, hosted by Andrew Hopkins (Dir System Technology at Arm), Kurt Shuler (VP marketing at Arteris IP) and Jens Benndorf (Managing Dir and COO at Dream Chip Technologies). The topic was implementing ISO 26262-compliant AI SoCs with Arm and Arteris IP, highly relevant since more and more of this class of SoC are appearing in cars. One thing that really stood out for me was the value of platform-based design in this area, something you might think would be old news for SoC design but which introduces some new considerations when safety becomes important.

A key aspect of platform-based design is being able to combine IP from multiple sources with differing levels of compliance to certain expectations, notably safety in this case. This can be most noticeable when you want to design part of the architecture to an ASIL D (safety critical) level while having enough safety diagnostic coverage to achieve ASIL B or C capabilities in other parts of the design. Designing an IP to this level entails a lot of overhead which may not be justified for safety-nominal (ASIL A/B) or even safety-indifferent (QM) components that you may want to use in your design.

How then can you get your SoC to higher ASIL compliance? The answer lies in being able to ensure that safety-nominal systems cannot corrupt safety-critical functions and can be tested or taken offline if they malfunction. This is all significantly mediated by the network between the IPs, as indicated in the figure above. Among other functions this requires health monitoring for all components and of course reporting faults to a safety controller which can channel problems upstream to decision-making functions (are we in trouble, should the driver grab the wheel, pay special attention, pull the car over to the side of the road?).

Monitoring functions (all provided through or together with the interconnect) include time-out checks for data requests, IP isolation through powering down the appropriate NoC socket connection to run live LBIST checks (at suitable times), and finally end-to-end ECC error detection/correction.

This ability to monitor, check and isolate faulty IP provides the means to ensure ASIL B,C or D compliance at the system level, but depends also on a “cannot-fail” subsystem called a safety island. This is a special function designed fully to ASIL D requirements, with lockstep CPUs, independent memories and run-time testable cache and many more mechanisms to ensure independence from the rest of the system. This safety island continuously monitors for faults and will report (at presumably programed levels of concern) to higher-level decision-making functions in the car.

Closing the loop, Jens talked about a reference platform design they have built at Dream Chip using these capabilities and how that has been spun into several production derivatives. The reference design is based on a quadcore A53, an ISP and vision processor, peripherals and memory interfaces, all connected through an Arteris IP Resilient NoC, together with the safety island. They have a cool demo of this functioning in an autonomous car according to Kurt.

Derivatives modify this platform with different numbers of CPUs in the cluster and different IP subsystems for the vision processor (GPU, NPU or a simpler processor) for active mirror replacements, front-camera and radar applications. In a pre-safety platform, spinning these derivatives would be no big deal. For systems requiring a higher ASIL (B, C, or D), it is a big deal and what makes it possible is this safety modularity around functions, the ability to monitor, isolate and ECC check through the interconnect and a carefully isolated safety island. All of these guarantee higher ASIL operation no matter what else in the SoC may go wrong.

You can learn more about this design by downloading the Arm TechCon presentation HERE.

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GLOBALFOUNDRIES and Arm Showcase Broad Range of Partnership

GLOBALFOUNDRIES and Arm Showcase Broad Range of Partnership
by Randy Smith on 10-21-2019 at 10:00 am
Categories: Events, Foundries, GlobalFoundries
1 Comment

I previously blogged on the GLOBALFOUNDRIES (GF) Technology Conference (GTC) held in Santa Clara, CA. The main takeaway that I shared in that blog was that GF’s announced “pivot” to a specialty foundry announced over a year ago, including its decision not to pursue 7nm and smaller nodes, appears to be working and GF is gaining momentum. There was not enough room in that blog to go into what I feel is another strategic decision GF made that is serving this transition well – its deep and broad relationship with Arm®. As many activities are going on between these companies, let me first break this into two broad categories – foundation IP and computing IP.

To have a thriving ecosystem on any given manufacturing process requires a strong collection of base-level IP, including standard cells, IO cells, memory compilers, and other basic building blocks. Collectively, I refer to this as foundation IP. Other IP providers and GF customers build their IP on top of the foundation IP. In my opinion, and I am admittedly biased1, TSMC’s rapid rise from $387M quarterly revenue in Q1 1998 to $2.5B by Q2 2006, coincided with its decision to have much of its foundation IP supplied by Artisan Components starting with TSMC’s 0.25-micron process in March of 1998. Arm announced its acquisition of Artisan® in August 2004. The foundry model took off in part due to the availability of foundation IP that was as good or better than what semiconductor manufacturers were developing themselves.

As a specialty manufacturer, GF has a large collection of processes. GF needs to make sure each process has a solid IP foundation. More than that, since each process is intended for a different field of use, that foundation IP should be tailored for the specific needs of designers using that process (e.g., low power design for a low power process, etc.) – a generic library is not very helpful. Along those lines, last month GF announced its 12LP+ solution, which makes use of Arm Artisan physical IP and ARM POP™  IP (more on POP IP later in this blog). These libraries are available now, and tape-outs are expected in 2020.

Arm Comprehensive Physical IP Platform at GF 12LP

  • Two logic library architectures (SC7.5, 9)
  • Nine memory compilers
  • GPIO for 1.8V and 3.3V
  • Specially optimized single rail 0.55V low-voltage compilers
  • Single-Fin Logic libraries to enable lowest power designs

Just two months ago, GF and Arm announced that they had taped out “an Arm-based 3D high-density test chip that will enable a new level of system performance and power efficiency for computing applications such as AI/ML and high-end consumer mobile and wireless solutions.” This unique project made use of breakthrough technology from both companies to come up with a more advanced packaging solution that should benefit GF customers needing a lower latency, higher bandwidth solution for applications such as AI and ML.

Gus Yeung

At GTC, there was a joint presentation by Ted Letavic, GF VP and Senior Fellow and Gus Yeung, GM VP and Fellow, Physical Design Group, Arm. Ted spoke about many innovations GF is developing under its specialty strategy, including IP coming from many other IP suppliers. There was again the GF Innovation Equation, which was prominent throughout the event and featured IP as a multiplier in supplying innovation to GF customers. Gus focused a bit more on ML,

Ted Letavic

showing the path Arm and GF are taking together in this rapidly evolving market. The partnership also includes Arm’s POP IP, which is a core-hardening acceleration technology. POP gives you Arm’s expertise captured in a way to accelerate your implementation of specific Arm cores while minimizing area, leakage, and dynamic power while also optimizing performance.

There is so much going on between GF and Arm, that I am sure to have left some things out. This relationship is certain to benefit both companies, and I am looking to further progress they can achieve together.

1 Randy Smith previously served as Artisan Components Director, Japan Sales, and Vice President of Corporate Ventures.

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WEBINAR: PAVE360 Validating Autonomous Vehicle Behavior

WEBINAR: PAVE360 Validating Autonomous Vehicle Behavior
by Daniel Nenni on 10-21-2019 at 6:00 am
Categories: Automotive, EDA, Events, Siemens EDA

Siemens Mentor recently announced PAVE360™, a very cool comprehensive pre silicon simulation environment. Autonomous cars are very popular here in Silicon Valley and quite safe on the highways since the average speed is 25mph (horrible traffic). In the city you need autonomous parking unless you want to waste precious time scavenging for a spot and climbing out your window since spaces continue to shrink and cars continue to grow. Kind of like airline seats.

The problem is that the lines of software code that power these new vehicles is increasing exponentially and validating the silicon and software integration is incredibly time consuming. I was very fortunate to work for one of the brilliant minds behind silicon simulation and I am honored to quote him here:

“PAVE360 represents the first output of an innovation process born from the combination of Mentor and Siemens employees, ideas, and technologies two years ago,“ said Ravi Subramanian, vice president and general manager of the IC Verification Solutions Division of Mentor, a Siemens business. “PAVE360 from Siemens delivers a comprehensive program to support the deep, cross-ecosystem collaboration necessary for our customers to develop powerful custom silicon and software solutions to power the autonomous vehicles revolution.“

To dig into PAVE360 further I organized a webinar with Mentor. I hope to see you there:

WEBINAR: PAVE360 Validating Autonomous Vehicle Behavior

Abstract: Validating an SoC for intelligent vehicles requires much more than conventional methodologies have used. In fact, correctness is only defined in the context of the physical environment, vehicle dynamics and occupant survivability. Mentor/Siemens’ PAVE360 addresses this complexity with a holistic engineering methodology pioneered by the smartphone industry and refined to apply to intelligent vehicles.

Presented by David Fritz: With over 25 years of experience in the Semiconductor industry having held senior technical roles at NVidia, Qualcomm, Texas Instruments, and others, Mr. Fritz leads the global autonomous IC and validation initiative at Siemens Mentor. Mr. Fritz brings innovation and entrepreneurial drive of fast moving Silicon Valley companies to the Siemens Mentor team by applying transformative technologies to the challenges of autonomous and connected vehicles.

About PAVE360
Democratizing Automotive IC Design and Development
As advances in processing continue to play an increasingly prominent role in automotive evolution, carmakers are turning to custom silicon designs to deliver the “just right” blends of cost, power, performance and advanced features necessary to enable an autonomous future.

With PAVE360, chip design can be democratized, enabling carmakers, chipmakers, tier one suppliers, software houses and other vendors to collaborate on the development and customization of extraordinarily complex silicon devices for autonomous vehicles. PAVE360 delivers a robust platform for this collaboration, helping to speed chip design and software validation, and enabling the creation of model-specific silicon for the first-generation of self-driving cars.

PAVE360 establishes a design-simulation-emulation solution that scales from individual blocks of a system-on-chip’s (SoC’s) IP, to hardware and software on the SoCs, to vehicle subsystems, and up through deployment of vehicles in smart cities – a true “chip-to-city” approach based on the increasing digitalization of the automotive industry.