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Samsung 2019 Technology Day Recap!

Samsung 2019 Technology Day Recap!
by Daniel Nenni on 11-01-2019 at 6:00 am

Samsung is a complicated company with a VERY long history. We attempted to capture the Samsung Experience in chapter 8 of our book “Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices”. If you are a registered SemiWiki member you can download a free PDF copy in our Books section.

Here is the chapter 8 introduction:

To Seoul, via Austin

Conglomerates are the antithesis of focus, and Samsung is the quintessential chaebol. From humble beginnings in 1938 as a food exporter, Samsung endured the turmoil and aftermath of two major wars while diversifying and expanding. Its early businesses included sugar refining, construction, textiles, insurance, retail, and other lines mostly under the Cheil and Samsung names.

Today, Samsung is a global leader in semiconductors, solid-state drives, mobile devices, computers, TVs, Blu-ray players, audio components, major home appliances, and more. Hardly an overnight success in technology, Samsung went years before discovering the virtues of quality, design, and innovation. The road from follower to leader was long and rocky.

And here are the final thoughts of the chapter:

A bigger question is how Samsung, and others, continue to innovate in smartphones beyond just more advanced SoCs. There are also other areas of growth, such as smartwatches and the IoT, where Samsung is determined to play. There are me-too features, such as Samsung Pay, and new ideas like wireless charging and curved displays. (More ahead in Chapter 10.)

How this unfolds, with Samsung both supplier and competitor in an era of consolidation for the mobile and semiconductor industries, depends on adapting the strategy. Innovations in RF, battery, and display technology will be highly sought after. Software capability is already taking on much more importance. As Chinese firms improve their SoC capability, the foundry business may undergo dramatic changes – and the center of influence may shift again.

 History says Samsung invests in semiconductor fab technology and capacity during down cycles preparing for the next upturn. Heavy investments in 3D V-NAND flash, the SoC foundry business, and advanced processes such as 10nm FinFET and beyond are likely to accelerate, and competition with TSMC and other foundries will intensify as fab expenses climb.

This book was published in December of 2015 and while there have been lots of changes at Samsung many things remain the same. Remember, they have the full support of South Korea including the government and more than 51 million people.

Bottom line: Samsung is a brute force technology innovator and we are very lucky to have them as a leader in the semiconductor industry, absolutely!

The Samsung Technology Day featured three key announcements introduced by the president of Samsung Semiconductor:

“Samsung is focused on harnessing the most advanced semiconductor technologies to power innovation across key markets,” said JS Choi, president, Samsung Semiconductor. “From System LSI devices that are perfectly adapted for real-world 5G and AI, to advanced solid-state drives (SSDs) that handle mission-critical tasks and offload CPU workload, we are determined to deliver infrastructure capabilities that are built to enable every wave of innovation.”

  • Exynos 990 and 5G Exynos Modem 5123:Delivers unprecedented AI-powered user experiences on-device with a dual-core neural processing unit (NPU) and enhanced digital signal processor (DSP) that can perform over ten-trillion operations per second. The Exynos 990 and 5G Exynos Modem 5123 harness the most advanced chipmaking technologies to-date with a 7-nanometer (nm) process using extreme ultraviolet (EUV) lithography.
  • Third-generation 10nm-class (1z-nm) DRAM:Delivers the industry’s highest performance, energy efficiency and capacity, since mass production in September. Optimized for premium server platform development, the 1z-nm DRAM will open the door to a lineup of memory solutions at the cutting-edge such as DDR5, LPDDR5, HBM2E and GDDR6 products as early as the beginning of next year.
  • 12GB LPDDR4X uMCP (UFS-based multichip package): Combines four 24Gb LPDDR4X chips and an ultra-fast eUFS 3.0 NAND storage into a single package, breaking through the current 8GB package limit in mid-range smartphones and bringing more than 10GB of memory to the broader smartphone market.

Personally, I found the event well organized and the presentations very well done. They were personalized and entertaining. One of the comments was that Samsung will dramatically increase their cloud silicon business. Currently they have 0% market share so the sky is the limit, literally.


BittWare PCIe server card employs high throughput AI/ML optimized 7nm FPGA

BittWare PCIe server card employs high throughput AI/ML optimized 7nm FPGA
by Tom Simon on 10-31-2019 at 6:00 am

Back in May I wrote an article on the new Speedster7t from Achronix. This chip brings together Network on Chip (NoC) interconnect, high speed Ethernet and memory connections, and processing elements optimized for AI/ML. Speedster7t is a very exciting new FPGA that can be used effectively to accelerate a wide range of processing tasks. Naturally with an announcement like this, the question of how to deploy this chip arises. Not everyone who could benefit from this new technology has the skills, time or resources to build it into a system. Data center operators who want to deploy this chip need a ready-to-go accelerator to make this happen.

Fortunately, Achronix just announced a major design win for their Speedster7t that will help end users get this chip into their server farms and data centers. Achronix and BittWare, a subsidiary of Molex, have teamed up to produce the VectorPath S7t-VG6 Accelerator Card. With it there is now an enterprise class PCIe accelerator card that can be used to provide best in class FPGA acceleration for cloud and edge computing.

The trend of adding data center accelerators has been heating up recently and the annual market is estimated to be around $2.8B for 2019. Forecasts have this growing to around $21B by 2023. Of this, the FPGA accelerator segment should be the fastest growing with a size of over $5B by 2023. This is because FPGA based accelerators hit on every cylinder when it comes to meeting business and technical needs.

FPGA accelerators offer very high performance per watt for a number of applications. Because they are reconfigurable, they allow the agility to take advantage of new algorithms or to be adapted for new applications. Because the BittWare VectorPath S7t-VG6 uses PCIe, it is easily scalable with the addition of any number of needed cards. Deployment is made easy with a full suite of development tools and BittWare’s support resources.

The VectorPath S7t-VG6 is a full height ¾ length (GPU size) double wide card with passive, active or liquid cooling options. The on-board hardware is well thought out. There is 8GB of 4Tbps GDDR6 as well as 4GB of DDR4. The PCIe interface is Gen3 x16. The card is expected to support Gen4 with qualification. The Ethernet interfaces use hard MAC and FEC IP that support a wide range of standard protocols and line rates. There is a 1x 400GbE interface that can be configured as 2x 200, 4x 100, or 8x 10/25/40/50GbE. There is also a 1x 200BgE interface that can be configured as 2x 100 or 4x 10/25/40/50GbE

To make the card even more useful there are clock and interface expansion options. On the front of the card there are clock inputs for 1PPS + 10MHz. On the back there are 3.3V GPIOs that are useful for control, triggers and adding support for legacy interfaces. Additionally, on the back there is an OCuLink expansion port that adds a lot of flexibility. It can be used for PCIe Gen4 or for general purpose SerDes. It offers low latency card-to-card connections for deterministic scaling. Or, it can be used at add extra network ports, add NVMe FLASH, or to define custom serial I/O interfaces.

The news release from Achronix and BittWare has a lot more information about customization options, developer’s toolkit and goes into more depth on the advantages of the Speedster7t FPGA. One of the key take-aways is that BittWare has the resources and technology to make deployment of the S7t VG6 accelerator card practical for a wide range of end users. I suggest looking at the full release on their websites to get more information.


Efficiency – Flex Logix’s Update on InferX™ X1 Edge Inference Co-Processor

Efficiency – Flex Logix’s Update on InferX™ X1 Edge Inference Co-Processor
by Randy Smith on 10-30-2019 at 10:00 am

Last week I attended the Linley Fall Processor Conference held in Santa Clara, CA. This blog is the first of three blogs I will be writing based on things I saw and heard at the event.

In April, Flex Logix announced its InferX X1 edge inference co-processor. At that time, Flex Logix announced that the IP would be available and that a chip, InferX X1, would tape out in Q3 2019. Speaking at the fall conference, Cheng Wang, Co-founder and Senior VP of Engineering, announced that indeed, the chip did tape out in Q3. Also, Cheng said that first silicon/boards would be available sometime in March 2020, there would be a public demo in April 2020 (perhaps at the next Linley Conference?), and that mass production will be in 2H 2020. While this means that Flex Logix is delivering on the announced schedule, there was certainly a specific focus to Cheng’s presentation beyond that message. In a word – Efficiency.

In engineering fields, we often compare different efforts or approaches to the same problems using benchmarks. When it comes to looking at finished products, these benchmarks can be straight-forward. For example, we review miles per gallon, acceleration, stopping distance, and other factors when analyzing the performance of a car. For processors, it has always been a bit more difficult to do benchmarking. I remember working with BDTi nearly 20 years ago when trying to compare the performance of various processors for video processing with widely different architectures. It took an organization like BDTi to give an unbiased analysis, though it was still challenging to see how the results related to your real-world needs.

There is an increasing number of processing options now being developed and deployed for neural network inference at the edge. More and more, we see attempts to standardize the benchmarks for these solutions. One example is Stanford University’s DAWNBench, a benchmark suite for end-to-end deep learning training and inference. But reading through this information, you still will come to realize that it is your specific application that truly matters. Why look at benchmark results for “93% accuracy”, if you must meet “97% accuracy”? Does Resnet 50 v1 accurately represent the model you will be running? In particular, DAWNbench was ranking results based on either cost or time. As engineers though we typically face criteria in a different manner – hard constraints and efficiency.

Hard constraints are easy to understand when looking at these benchmarks as there will be simple constraints for area, power, and performance. Likely, multiple architectures may be able to meet all or most of these constraints, though perhaps not simultaneously. But to understand which approach meets them best, you need to consider efficiency – inferences per $, and inferences per watt. This method of showing performance is where Flex Logix’s InferX X1 approach seems to separate itself from the competition, at least for the devices shown. From the Flex Logix presentation at the Fall Conference:

DRAM costs money, so it is important to be efficient in your use of DRAM. If you are not considering DRAM efficiency in making your selection of IP, then you are not measuring your true costs. The DRAM requirements to hit a certain performance level are not equal between the various processors.

The one thing that has been clear to me this year, especially having attended both the AI Hardware Summit and the Linley Fall Processor Conference, is that simply measuring TOPS is a waste of time. See below the information presented by Flex Logix on TOPS across a few well-known solutions. In this example, InferX X1 would seem to be a minimum of 2x more efficient than the Nvidia solutions.

The entire Linley Fall Processor Conference presentation from Flex Logix is available on their website here. It is not possible to share all the details in a blog here, but I encourage you to see the entire presentation. There is more information available in the presentation about how this efficiency is achieved and how to accurately predict inference performance (how Flex Logix confirmed their performance pre-silicon).


Arm Reveals Custom Instructions, Mbed Partner Governance

Arm Reveals Custom Instructions, Mbed Partner Governance
by Bernard Murphy on 10-30-2019 at 6:00 am

Tipping the scale

At TechCon Arm announced two more advances against competitive threats, one arguably tactical and the other strategic, at least in this writer’s view.  The tactical move was to add support for custom instructions, the ability to collapse multiple instructions into a single instruction through customer-added logic which hooks into the CPU pipeline. This supports customer differentiation in performance and low power consumption for IoT devices, for example for trig functions used in GPS location. Software developers access these new functions as intrinsics apparently.

Custom instruction capability has been around for a while, especially in DSP IPs (where I believe it is extensively used for vectorized operations) and more recently and obviously in the RISC-V architecture. Of course in RISC-V you can do anything because it’s an open ISA but I imagine you may need to curb your enthusiasm for over-exotic capabilities if you want to remain compliant with the ecosystem. Perhaps then the customization advantages over the Arm offering will not be so great.

Custom instruction support will initially be provided in Cortex-M33, available in the first half of 2020, and will be extended further in the Cortex-M family at a later date. The capability comes at no additional cost for new and existing licensees. Further ability to differentiate at no added cost would I imagine give pause to anyone thinking about a switch to a different architecture.

The more strategic move is in opening up the governance of the Mbed OS to silicon partners. The ecosystem has always been a powerful advantage for Arm and will (in my view) remain a major hurdle for any competing solutions. They have equally built a big ecosystem over the last 10 years around their open-source IoT operating system, Mbed OS (about half a million third-party software developers and 150 Mbed-enabled boards and modules so far).

So far that’s been under Arm’s direction. Apparently silicon partners have been asking for more insight and input into Mbed OS future directions. Arm proposed this new governance approach which was well received and is now implemented in a technical working group and a product working group. The product working group meets monthly to prioritize and vote on new capabilities. As one example they’re already working on new low-power battery optimizations based on contributions from partners. Analog Devices, Cypress, Maxim Integrated, Nuvoton, NXP, Renesas, Realtek, Samsung, Silicon Labs and u-blox, among others, are already active in the WG and any Mbed silicon program partner is welcome to join at no cost.

This is strategic because will help further establish the ecosystem and technical investment partners make in a solution. In turn they’ll become more and more unwilling to drop to switch to another solution which may not provide all those nice features ready-made. Not to say that Arm (or the competition) couldn’t cross a line at some point where a switch would become more compelling. But so far at least, Arm seems to be making all the right moves to reinforce their position, conceding just enough in tactical areas while continuing to reinforce their strategic advantages. They continue to impress me as a thoughtful and well-managed company. They just keep adding more reasons to tip the scale in their direction.


“Connecting the Divide” at SEMICON Europa

“Connecting the Divide” at SEMICON Europa
by admin on 10-29-2019 at 2:00 pm

Connecting the Divide between Design and Manufacturing is an overarching theme within the ESD Alliance as these two essential semiconductor disciples become more reliant on each other. It’s also the reason we’re hosting  SMART Design, the first system-centric series showcasing advances in electronic system design to be held at SEMICON Europa held November 12 through November 15 in Munich, Germany.

SMART Design’s program, “Designing Electronic Systems for Future Applications,” includes presentations and a panel discussion underscoring how the increasing applications of advanced electronic system designs including automotive and medical pose new challenges that demand closer collaboration between design and manufacturing. Our goal is to create an opportunity for attendees to deepen their understanding of the links across Design and Manufacturing and throughout the supply chain. This will foster the collaborations essential to addressing technical challenges and ushering exciting new electronic products from concept to consumer.

The 2.5-hour program begins with Babak Taheri, Silvaco’s CEO and CTO, who will assess “Next Generation SoC Design: From Atoms to Systems.” “Near-Threshold Logic Benefits the Full Application Stack,” will be addressed by Lauri Koskinen, CTO of Minima Processor. Next up will be “Deep Learning for Electronics Manufacturing” by Javier Cabello, software and vision engineer at Mycronic AB.

“Cloud-Accelerated Innovation for Semiconductor Design and Verification,” a topic of interest to a wide audience, will be given by David Pellerin, head of worldwide business development, Hitech/Semiconductor for Amazon Web Services. Ian Campbell, OnScale’s CEO, follows with another talk on cloud-based Design titled, “Cloud Engineering Simulation: A Game Changer for Engineers.” The last presentation before a panel session is titled, “Addressing the ‘New-Space’ Paradigm Shift in Development and Production of High Reliability, Space Grade Semiconductor Components.” The presenter will be Christian Sayer, field applications engineer from Cobham Advanced Electronics Solutions.

Noted industry executive Jim Hogan, managing partner of Vista Ventures, will moderate “The Risk of Obsolete Design and Verification Environments in the RISC-V Era,” an ideal topic in the open-source era. Panelists include Gabriele Pulini, senior business development manager at Mentor, a Siemens Business; Silvaco’s Babak Taheri; Adnan Hamid, Breker Verification Systems’ CEO; Raik Brinkmann, president and CEO at OneSpin; and Paul Cunningham, corporate vice president and general manager of the System Verification Group from Cadence Design Systems, Inc.

SMART Design is scheduled for Thursday, November 14, from 2:30 p.m. until 5 p.m. in TechARENA 1, Hall B1. A networking hour hosted by the ESD Alliance and SEMI immediately follows.

Also debuting this year at SEMICON Europa is the SMART Transportation Forum led by SEMI’s Global Automotive Advisory Council (GAAC) with presentations from the Design, semiconductor equipment and materials suppliers and automotive OEM communities. The SMART Transportation Forum, “Connected-to-Everything Automated Mobility,” will be held Wednesday, November 13, from 9:30 a.m. until 3:30 p.m. in Room 14C at International Congress Center Munich.

As the SMART Design program offers, “Connecting Design and Manufacturing” is not only a catchphrase. While Design may be where electronics begins, it’s not the whole picture. With the complexity of systems being designed and manufactured, connecting Design and Manufacturing must be more than just talk. Connecting them will enable smarter, faster, more powerful, smaller, more reliable and more affordable electronic products produced by the $2-trillion global electronic product manufacturing and supply chain. This is a huge responsibility. Meeting it demands cooperation and collaboration across multiple disciplines including semiconductor Design, packaging, software development, materials and manufacturing, system integration and testing.

We look forward to seeing Semiwiki readers at SMART Design at SEMICON Europa as we extend design expertise in the worldwide electronics industry by “Connecting the Divide between Design and Manufacturing.


Synopsys’ New Die-to-Die PHY IP – What It Means

Synopsys’ New Die-to-Die PHY IP – What It Means
by Randy Smith on 10-29-2019 at 10:00 am

This morning, Synopsys announced its new Die-to-Die PHY IP. This announcement is critically important as it addresses two major market drivers – the growing need for faster connectivity in the datacenter and similar markets, and a path to better exploit the latest processes by dealing with yield issues for larger dies in a different manner. Also, this seems to be just the first step in this area, and we will anxiously await further advances in die-to-die connectivity. I believe Synopsys is trying to take the lead here and potentially help drive for industry standards that do not yet exist. Please read the press release for the details. Below, I will focus on what solutions this announcement can enable for use by chip architects and designers.

I have written a few times in the past few months on SerDes and other high-speed connectivity paths in the datacenter. Given the seemingly ever-growing demands for cloud computing, whether in e-commerce, machine learning, AI, gaming – the list is growing daily – datacenter administrators are hungry to find ways to deliver high performance. This pursuit has seen many gains in PCIe (inside the chassis), computer-to-computer, rack-to-rack, and datacenter-wide areas. High-speed optical solutions are now targeting high-speed in lengths up to 10 km. But these solutions still come with some latency and area penalties that make them prohibitive for a die-to-die solution.

By being able to connect multiple dies on a substrate in a point to point manner using the new Synopsys die-to-die PHY, which is available now, you can create a larger piece of functionality with less latency between the blocks. Admittedly, there has not been enough standardization for this type of solution. BGA-style connections within multi-chip modules (MCM) are not new, but there has not been much standardization of the PHYs connecting them. Initially, this solution will only be available on a single 7nm FinFET process, so it doesn’t yet support a heterogenous MCM solution. However, I expect that will certainly be coming soon. For now, this advancement alone is impressive.

As you make larger and larger semiconductor dies on the latest manufacturing processes, yield usually drops dramatically which significantly increases cost. If you take that same design and split it into multiple smaller dies in the same process you can see a huge saving in cost just from the improved yield. To achieve lower cost, the saving from the yield need only be more than the additional cost of the substrate used to connect the dies. If the original die was already going to sit on a substrate, then this is an easy decision. If not, it is still an option worth exploring as it may very well be less expensive to produce.

Another interesting consideration is what this technology can enable in conjunction with other technologies. For example, I can envision a design where multiple chiplets are placed in a row on a substrate forming a datapath (e.g., data flowing left to right, from die to die). If you need chunks of nearby memory, you have a choice, north or south of the datapath elements on the substrate, or can you place the memory on top of the datapath element, perhaps using another substrate? In other words, can you have BGA connection above and below the die? It is an interesting thought. Of course, that may also bring up thermal and other EM considerations. The use of stacked die is not a new thought. So how far can we take this new development from Synopsys? My imagination is started to run wild.

“1.8 terabit-per-second per millimeter unidirectional bandwidth for high throughput die-to-die connectivity.”

“One picojoule per bit (pJ/bit) for ultra-low-power.”

What will designers due with that? We should all be excited to find out.

Related Blog


New ARC VPX DSP IP provides parallel processing punch

New ARC VPX DSP IP provides parallel processing punch
by Tom Simon on 10-29-2019 at 6:00 am

The transition to the digital age from a mostly analog world really began with the invention of the A-to-D and D-to-A converters. However scalar processors can easily be overwhelmed by the copious data produced by something as simple as an audio stream. To solve this problem and to really jumpstart the digital age, the development of the digital signal processor (DSP) catalyzed the sweeping changes we are still witnessing today. If you are old enough, you probably remember when early DSPs were added to audio systems to enhance sound. Because of their immense usefulness, the applications of DSPs have expanded to include an ever-growing list of domains. However, it is a safe generalization to say that they’re more most useful in helping computing systems deal with the external world.

With applications as diverse as RF signal processing, automotive sensor RADAR, LIDAR, sensor fusion, vision, and in some cases machine learning, DSPs have needed to support a wider range of operations and increasing parallelism. To help SoC designers meet these challenges Synopsys has just introduced the impressive ARC VPX family of DSP Processor IP. The two new entrants in this family are the VPX5 and a Functional Safety version called the VPX5FS. So, what makes these DSPs different?

The answer in a word is parallelism at every level. Each VPX core offers 4 VLIW execution slots. VLIW introduces parallelism with the ability to encode multiple instructions for parallel execution in the same process or cycle. VLIW can be tricky to program because intermediate results in long expressions need to be cascaded through multiple VLIW operations. However, Synopsys has announced ARC MetaWare Tools that hide the mechanics of VLIW operation from developers, so they can write C++ code as usual and reap the benefits of VLIW acceleration.

The next level of parallelism for the VPX DSP IP cores is support for SIMD. SIMD lets one instruction operate on many (up to 512 for VPX5) data items. Three of the VLIW slots support SIMD, providing massive acceleration. Once again, Synopsys has made sure that the ARC MetaWare Tools help software developers easily take advantage of SIMD with minimal effort.

On top of this, VPX can scale up to 4 cores, adding a third layer of parallelism in VPX based SoCs. This ‘three dimensional’ parallelism gives the VPX based SoCs the ability to tackle a range of problems far beyond the now seemingly quaint uses for the first generations of DSPs.

A trend in machine learning, where parallel processing pays off, is the to move toward 8 or 16 bit integer operations to speed ML recognition algorithms. However, the real world is a messy place filled with data that can only be characterized by floating point values. Before a ML algorithm can be applied, high quality sensor data is needed, often in the form of sensor fusion output, to properly characterize what is happening in the real world. Floating point data offers high dynamic range and higher accuracy than integer values. The VPX cores support floating point operations in their VLIW slots. To further help with processing, VPX offers a linear algebra math unit that can perform sine, cosine, arctan, sqrt, log, exponent and other operations. Of course, there is also a VLIW slot that can use SIMD on 8, 16 and 32 bit integer data.

In their announcement Synopsys highlights several key areas where they see the VPX DSPs playing an important role. They are LIDAR, RADAR, Sensor Fusion and 5G communications. The low power and configurability of the VPX cores mean that they can be applied where needed to help process enormous amounts of data. A result of having higher performance in the system is a potential reduction of sensors and sensor complexity. For 5G, where signal processing becomes more important because of channel complexity, additional processing power can help improve data rates and reduce power. The full announcement with more details on the VPX5 and VPX5FS can be found on the Synopsys website.


Cadence Shows off 5LPE Hercules Implementation

Cadence Shows off 5LPE Hercules Implementation
by Randy Smith on 10-28-2019 at 10:00 am

In a joint presentation given by Samsung, Arm, and Cadence at the Arm TechCon event on October 9, 2019, Cadence showed some results and explained its collaboration project used to implement the new Arm Hercules CPU on Samsung’s advanced 5LPE process. I do not want to minimize the significance of Samsung’s and Arm’s participation in this process. Samsung’s work in properly characterizing this cutting-edge process and Arm’s multiple contributions to the project, including its POP IP, which greatly aids in the implementation of Arm processors, were critical to the success of the project. But, if you have already selected the process and core, then it is tools that are the variable. Therefore, this blog will focus on Cadence’s efforts at implementing the Hercules core in this process.

The presenters at the event were Kevin K. Yee (Samsung), Fakhruddin Ali Bohra (Arm), and Edson Gomersall (Cadence). At the beginning of Edson’s portion of the talk, Edson readily acknowledged the critical importance of the contributions of his other partners in the projects. In particular, he stressed the importance of the tuning between the Arm IP and the Cadence tools, as seen in the diagram below.

The support Cadence received from Samsung was also important as there is typically a lot of tool tuning to be done for a new manufacturing process. This pioneering project enables better “out of the box” results for mutual customers looking to implement this core on this process for their designs. ‘Global route tuning,’ and ‘layer promotion adherence’ were two areas Cadence focused on in the discussion.

As I mentioned in the initial paragraph, the contributions of all three members of the project were critical to the success of the project. And I believe the project has paved the way for customers of these companies to implement this core on the process successfully. Nevertheless, designers will want to know which EDA toolset is best to work with to implement this core on this process. I think it is too soon, and not enough information is being published yet, to give a definitive answer – but we can see Cadence’s strengths.

Design optimization has been part of Cadence’s DNA since its very initial acquisition in 1989, Tangent Systems (I was a co-founder of Tangent). Up until the time of Tangent’s first product release, TANCELL, all placement and route implementations only focused on minimizing area while completing all the connections without design rule violations. In other words, before TANCELL, the only thing being optimized was area. TANCELL was the first commercial timing-driven layout tool. It would analyze the timing of a design (using static timing analysis) to prioritize the wire length of timing critical nets. This optimization was considered in every design step – global placement, global routing, detailed placement, and detailed routing. It was a crucial initial step, but it put Cadence miles ahead of the competition and developed an engineering culture of co-optimization.

Physical design tools have become much more sophisticated now. From an optimization perspective, they minimally need to optimize for Power, Performance, and Area (PPA). In reality, it is now far more complicated than that. ‘Power’ does not only mean power consumption. IR drop is an important consideration. Wire length is far from the only goal in routing as now crosstalk considerations must be addressed. There are many more concerns beyond this, and Cadence is addressing them all.

There are two principal techniques to optimize a layout result – concurrent analysis and design optimization. Design optimization is the older technique, though it still has its place. In design optimization, you analyze a competed design, target areas to improve, try to improve it, then reanalyze the design. This loop continues until you have an acceptable result. This technique usually works, but not always. A more effective approach is concurrently analyzing the design as you are impending it. To make this work, you should analyze it with the actual signoff tool, not some simplified model. Cadence can do this as it has the signoff tools.

Cadence, Samsung, and Arm seem to have worked together quite well on this project. It will be interesting to hear more when benchmark results start to become available. Learn more about Innovus here.


DAC 2020 – Call for Contributions

DAC 2020 – Call for Contributions
by Daniel Payne on 10-28-2019 at 6:00 am

57DAC in SFO

My first DAC was in 1987 so I’ve seen our industry expand greatly over the years, and I expect that #57DAC on July 19-23, 2020 in SFO to be another exciting event to attend for semiconductor professionals from around the globe. What makes DAC so compelling for me to visit are the people, exhibitors, panel discussions, technical presentations and industry buzz that you just cannot glean from a blog or glossy brochure.

Let me just summarize all of the contribution deadlines to get you thinking about what you could share with the rest of us:

The topic domains for 2020 at DAC include the following seven areas:

  • Design
  • EDA
  • Embedded Systems & Software
  • Machine Learning, AI
  • Security
  • Autonomous Systems
  • Semiconductor IP

You can even submit a panel proposal in one of four categories:

  • Research
  • Designer Track
  • IP Track
  • Embedded Systems

I hosted a panel discussion on SPICE circuit simulators a few years back, and it was a learning experience to invite four panelists from CAD and design backgrounds to answer my questions and even audience questions about the state of the art.

To teach other engineers something new in about 1.5 to 3 hours, consider a tutorial proposal.  These tutorials are delivered on Monday, July 20th. For a topic longer than a tutorial, consider putting on a workshop in up to 9 hours.

Finally, if you have a topic for a large audience that has both technical and business impact, consider submitting a DAC Pavilion proposal. These are either Panels or SKYtalk formats.

I look forward to seeing my friends, co-workers, EDA vendors, IP companies, foundries, plus industry movers and shakers in San Francisco for the 57th DAC. Submitting a proposal for DAC will certainly raise your personal and corporate profile and lead to advancement in our high-tech industry, so go for it and beat the deadline.

About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP), embedded systems and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design Automation (ACM SIGDA).


GM is Burning

GM is Burning
by Roger C. Lanctot on 10-27-2019 at 11:00 am

What is it about General Motors? The once largest maker of cars in the world (now sixth or seventh) has been in an all-fronts retreat for years – while Wall Street analysts and top GM brass whistle past the graveyard touting gains in the company’s stock price and profitability.

GM has exited key markets including Europe, India and South Korea, is winding down its passenger car business, and is even paring back startup operations such as Maven car sharing (eight cities shut down). Meanwhile GM’s Cruise Automation operation posts quarterly losses in excess of $250M.

With the United Auto Worker’s strike against GM entering its fifth week, Wall Street analysts express their “comfort” with an extended strike as long as “the ends justify the means,” in the words of one. We are all familiar with the technological, regional, and economic whipsaw facing GM – and other car companies – as a) production shifts to lower cost countries, b) electrification threatens internal combustion vehicle demand, and c) software developers are prioritized over factory workers.

But GM is an extreme case. At each turn, GM is rewarded for shrinking and pulling back, with the apparent goal of rewarding stockholders. What has been lost is a sense of mission. What is GM’s purpose, at the end of the day?

The UAW strike now darkening GM’s doorstep and rippling across the entire industry and supply chain is a clearly calculated measure representing merely the latest step in GM’s extended shrinkage program. It’s notable that at a time when GM is announcing ongoing plant closings a sticking point in the negotiations with the UAW are the size of plant investments – in addition to compensation and health care costs.

Since the arrival of Mary Barra as GM’s CEO “down” has become “up” for GM. The worse the news is, the better the stock performs. One can imagine senior GM executives glancing out of their office windows in the Renaissance Center in downtown Detroit – gazing off in the direction of idled factories and musing: “Do your worst, UAW!”

GM may be overlooking what it is truly up against in the global auto market of 2019. The company is up against a determined foe in the form of one Tesla Motors.

Tesla may currently be putting its biggest visible market share hurt on luxury auto makers from Germany, but the bigger hurt is coming from a talent bleed. For new college grads looking for inspiring automotive opportunities, Tesla offers a green carbon-free vision of automobile ownership and self- driving technology. And for its factory workers (who have had their share of disputes and opposition to management) the company offers growth and potential prosperity.

GM is doing its best to cull its share of new engineering grads with Cruise Automation. But GM can’t offer its line workers much of a vision of the future. The UAW strike is clearly a defensive rearguard action.

So the incredible shrinking GM is being sliced both ways. The company is trying to pivot to electrified vehicles – which will require system-wide factory shifts and further closures for sure – while preserving its purportedly profitable (in spite of massive incentives) SUV/truck/crossover business and exiting passengers vehicles. It must add expensive software talent, while tamping down compensation expectations along the production line.

The company must fund the future – electrified, self-driving vehicles – from the still-profitable husk of the internal combustion past with a restive, tortured workforce well aware of its future marginalization. In essence, the UAW is holding GM’s future hostage as a last resort as the company’s remaining production seeps away to Mexico, China, and other distant shores.

At five weeks, it appears that the stakes couldn’t be higher and GM’s resolve more determined. For all its alleged corruption and political vulnerability (UAW workers are estimated to be making $13 more per hour than workers at non-union U.S. plants – i.e. quit your complaining!), the UAW is likely responding to the awkward and contradictory picture GM brass has painted – pleading poverty after posting an $8B profit to the delight of Wall Street.

It’s hardly a surprise that the unions want a piece of that action and some commitment to their long-term needs – as they watch the incredible shrinking GM’s market share evaporate and plants close. In the end, it only seems fair. And in reality the strike appears to be a calculated risk that GM has chosen to take on – not the unions. There are no surprises in GM factories. The only surprise is how little anyone – not GM management, not the investors, nor the workers – seems to care. That’s the worst news of all out of the UAW strike. Does anyone – other than stressed out suppliers – care what happens to GM? Is GM, as the commentary on its Website suggests, just building memories?