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Cadence Shows off 5LPE Hercules Implementation

Cadence Shows off 5LPE Hercules Implementation
by Randy Smith on 10-28-2019 at 10:00 am

In a joint presentation given by Samsung, Arm, and Cadence at the Arm TechCon event on October 9, 2019, Cadence showed some results and explained its collaboration project used to implement the new Arm Hercules CPU on Samsung’s advanced 5LPE process. I do not want to minimize the significance of Samsung’s and Arm’s participation in this process. Samsung’s work in properly characterizing this cutting-edge process and Arm’s multiple contributions to the project, including its POP IP, which greatly aids in the implementation of Arm processors, were critical to the success of the project. But, if you have already selected the process and core, then it is tools that are the variable. Therefore, this blog will focus on Cadence’s efforts at implementing the Hercules core in this process.

The presenters at the event were Kevin K. Yee (Samsung), Fakhruddin Ali Bohra (Arm), and Edson Gomersall (Cadence). At the beginning of Edson’s portion of the talk, Edson readily acknowledged the critical importance of the contributions of his other partners in the projects. In particular, he stressed the importance of the tuning between the Arm IP and the Cadence tools, as seen in the diagram below.

The support Cadence received from Samsung was also important as there is typically a lot of tool tuning to be done for a new manufacturing process. This pioneering project enables better “out of the box” results for mutual customers looking to implement this core on this process for their designs. ‘Global route tuning,’ and ‘layer promotion adherence’ were two areas Cadence focused on in the discussion.

As I mentioned in the initial paragraph, the contributions of all three members of the project were critical to the success of the project. And I believe the project has paved the way for customers of these companies to implement this core on the process successfully. Nevertheless, designers will want to know which EDA toolset is best to work with to implement this core on this process. I think it is too soon, and not enough information is being published yet, to give a definitive answer – but we can see Cadence’s strengths.

Design optimization has been part of Cadence’s DNA since its very initial acquisition in 1989, Tangent Systems (I was a co-founder of Tangent). Up until the time of Tangent’s first product release, TANCELL, all placement and route implementations only focused on minimizing area while completing all the connections without design rule violations. In other words, before TANCELL, the only thing being optimized was area. TANCELL was the first commercial timing-driven layout tool. It would analyze the timing of a design (using static timing analysis) to prioritize the wire length of timing critical nets. This optimization was considered in every design step – global placement, global routing, detailed placement, and detailed routing. It was a crucial initial step, but it put Cadence miles ahead of the competition and developed an engineering culture of co-optimization.

Physical design tools have become much more sophisticated now. From an optimization perspective, they minimally need to optimize for Power, Performance, and Area (PPA). In reality, it is now far more complicated than that. ‘Power’ does not only mean power consumption. IR drop is an important consideration. Wire length is far from the only goal in routing as now crosstalk considerations must be addressed. There are many more concerns beyond this, and Cadence is addressing them all.

There are two principal techniques to optimize a layout result – concurrent analysis and design optimization. Design optimization is the older technique, though it still has its place. In design optimization, you analyze a competed design, target areas to improve, try to improve it, then reanalyze the design. This loop continues until you have an acceptable result. This technique usually works, but not always. A more effective approach is concurrently analyzing the design as you are impending it. To make this work, you should analyze it with the actual signoff tool, not some simplified model. Cadence can do this as it has the signoff tools.

Cadence, Samsung, and Arm seem to have worked together quite well on this project. It will be interesting to hear more when benchmark results start to become available. Learn more about Innovus here.