GLOBALFOUNDRIES and Arm Showcase Broad Range of Partnership

I previously blogged on the GLOBALFOUNDRIES (GF) Technology Conference (GTC) held in Santa Clara, CA. The main takeaway that I shared in that blog was that GF’s announced “pivot” to a specialty foundry announced over a year ago, including its decision not to pursue 7nm and smaller nodes, appears to be working and GF is gaining momentum. There was not enough room in that blog to go into what I feel is another strategic decision GF made that is serving this transition well – its deep and broad relationship with Arm®. As many activities are going on between these companies, let me first break this into two broad categories – foundation IP and computing IP.

To have a thriving ecosystem on any given manufacturing process requires a strong collection of base-level IP, including standard cells, IO cells, memory compilers, and other basic building blocks. Collectively, I refer to this as foundation IP. Other IP providers and GF customers build their IP on top of the foundation IP. In my opinion, and I am admittedly biased¹, TSMC’s rapid rise from $387M quarterly revenue in Q1 1998 to $2.5B by Q2 2006, coincided with its decision to have much of its foundation IP supplied by Artisan Components starting with TSMC’s 0.25-micron process in March of 1998. Arm announced its acquisition of Artisan® in August 2004. The foundry model took off in part due to the availability of foundation IP that was as good or better than what semiconductor manufacturers were developing themselves.

As a specialty manufacturer, GF has a large collection of processes. GF needs to make sure each process has a solid IP foundation. More than that, since each process is intended for a different field of use, that foundation IP should be tailored for the specific needs of designers using that process (e.g., low power design for a low power process, etc.) – a generic library is not very helpful. Along those lines, last month GF announced its 12LP+ solution, which makes use of Arm Artisan physical IP and ARM POP^™  IP (more on POP IP later in this blog). These libraries are available now, and tape-outs are expected in 2020.

Arm Comprehensive Physical IP Platform at GF 12LP

• Two logic library architectures (SC7.5, 9)
• Nine memory compilers
• GPIO for 1.8V and 3.3V
• Specially optimized single rail 0.55V low-voltage compilers
• Single-Fin Logic libraries to enable lowest power designs

Just two months ago, GF and Arm announced that they had taped out “an Arm-based 3D high-density test chip that will enable a new level of system performance and power efficiency for computing applications such as AI/ML and high-end consumer mobile and wireless solutions.” This unique project made use of breakthrough technology from both companies to come up with a more advanced packaging solution that should benefit GF customers needing a lower latency, higher bandwidth solution for applications such as AI and ML.

At GTC, there was a joint presentation by Ted Letavic, GF VP and Senior Fellow and Gus Yeung, GM VP and Fellow, Physical Design Group, Arm. Ted spoke about many innovations GF is developing under its specialty strategy, including IP coming from many other IP suppliers. There was again the GF Innovation Equation, which was prominent throughout the event and featured IP as a multiplier in supplying innovation to GF customers. Gus focused a bit more on ML,

showing the path Arm and GF are taking together in this rapidly evolving market. The partnership also includes Arm’s POP IP, which is a core-hardening acceleration technology. POP gives you Arm’s expertise captured in a way to accelerate your implementation of specific Arm cores while minimizing area, leakage, and dynamic power while also optimizing performance.

There is so much going on between GF and Arm, that I am sure to have left some things out. This relationship is certain to benefit both companies, and I am looking to further progress they can achieve together.

¹ Randy Smith previously served as Artisan Components Director, Japan Sales, and Vice President of Corporate Ventures.