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Semiconductor Expert Forum

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The New SemiWiki Job Board!

The New SemiWiki Job Board!
by Daniel Nenni on 11-09-2019 at 6:00 am
Categories: General

As a very experienced semiconductor job seeker/employer the most important lesson I have learned in 35 years is that getting the first interview is not so much WHAT you know as WHO you know. Networking really is the key to career success and SemiWiki 2.0 is all about networking, absolutely.

In fact, that is one of the reasons why I became a blogger. What I discovered when I started my career as a semiconductor ecosystem consultant is that I would spend more time looking for clients than actually doing the work which I found to be ridiculously inefficient. Once I started blogging and founded the SemiWiki platform I quickly established a sizable network that made consulting a very profitable career.

Given that, the first thing I would do as a job seeker, besides joining SemiWiki, is to focus on networking. Target specific companies and build a network of people who can assist you in that job search. In my experience the most successful job search is when you find a job before it is posted and the flood gates of resumes open. If not, sometimes applying for that first job opening leads to others so always persist. That is what networking is all about, building a career knowledge base and using it to your advantage.

As SemiWiki approaches its 9th anniversary and celebrates more than 3 million unique visitors we are happy to now include a job board in collaboration with our sponsoring companies who of course we are intimately familiar with. If you click on the Job Board icon in the header you can then search using keywords, location, or company name.   This is open to all job seekers, registered SemiWiki members or not. The SemiWiki job board will be updated daily with new opportunities.

If you are a SemiWiki member then please use the jobs forum discussion area to seek help with specific companies or openings. SemiWiki has more than 40,000 registered users and as a member you can also use the SemiWiki private email system for further discussions.

The best person to start with is me of course. I have the widest network inside the semiconductor ecosystem that you will ever experience. I am also a LinkedIn power user. If I don’t know the right person for your job search inside a company, I certainly know someone who knows the right person.

The semiconductor industry is transforming once again which leads to new career opportunities for semiconductor professionals. If you are relatively new to the industry download our book Fabless: The Transformation of the Semiconductor Industry. If you have questions drop me an email on SemiWiki and we can schedule a call to discuss. The same goes for experienced semiconductor job seekers. Let’s talk about the latest semiconductor industry transformation and how to leverage it for career growth.

The internal mantra for SemiWiki is “For the greater good of the semiconductor industry”. That is why we do what we do, absolutely. Regardless of your experience or circumstance, everyone needs support during a job search so let’s work together for the greater good.

Let’s start the conversation in the comments section and go from there…

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Mentor Adds Circuit Simulators to the Cloud using Azure

Mentor Adds Circuit Simulators to the Cloud using Azure
by Daniel Payne on 11-08-2019 at 6:00 am
Categories: Siemens EDA

Mentor and Azure

Most EDA tools started out running on mainframe computers, then minicomputers, followed by workstations and finally desktop PCs running Linux. If your SoC design team is working on a big chip with over a billion transistors, then your company likely will use a compute farm to distribute some of the more demanding IC jobs over lots of cores to get your work done in a reasonable amount of time. A clearly emerging trend is to consider running EDA tools in the cloud on an as-needed basis, because the cloud scales so easily, and you don’t have to buy all of that hardware and hire an IT group to support you.

I’ve been watching this cloud trend for several years now, and each quarter I see more EDA companies partnering with the major cloud vendors to help IC design teams get their work done smarter and faster than ever before. Mentor for example has cloud-enabled several EDA tools:

In this blog I’m focused on that last bullet point where Mentor recently announced that circuit design engineers can now simulate their SPICE netlists in the Azure cloud, scaling to 10,000 cores. The biggest application of this scaling would be for the task of library characterization flows, effectively shortening the wait time.

I spoke with Sathish Balasubramanian from Mentor last month to better understand why design teams need something like SPICE simulators in the cloud.  He talked about engineering teams using their own compute resources with maybe 200-300 cores, typically running library characterization for a week. Sathish then noted that the same library characterization workload could be run in the Azure cloud on up to 10,000 cores, reducing the compute time to about an hour.  OK, that sounds compelling to me.

Since library characterization and other AMS circuit simulation verification jobs are only run at certain times during a project, it starts to make sense to use a cloud-based vendor like Microsoft with their Azure offering, loaded with either Eldo or AFS circuit simulators.

Mentor has addressed the list of concerns that come up with running EDA tools in the cloud:

  • Security
  • Setup
  • Managing EDA tool licenses
  • Data transferral

I then asked Sathish a set of questions:

Q: Why choose Azure?

A: It’s all based on customer demand, Mentor also has a relationship with Amazon Web Services. Microsoft is a close partner with Mentor.

Q: What is the learning curve like?

It’s quick, like a couple of hours to setup the Azure environment and get started. Customers first setup their Azure account, then start deploying the characterization workload. We have  a configuration already setup for using Mentor library characterization tools, based on our Solido technology.

Q: Can I mix another vendor’s characterization tools with Mentor circuit simulators in the cloud?

A: At this time it’s an all-Mentor EDA tool flow in Azure.

Q: How efficient is it using Azure for circuit simulation jobs?

A: We can use up to 10,000 cores with a 91% linear scaling results, and it took some effort to reach that milestone.

Q: Who are the first customers of this cloud offering?

A: They are top 10 semiconductor companies and foundries, stay tuned for customer quotes.

Q: How do you manage all of those licenses?

A: The EDA tool licenses use Mentor’s FlexLM system, and then Microsoft has their pricing based on how many total CPU cycles you use.

Q: How do I find out about pricing?

A: Just contact your local Mentor Account Manager.

Q: Does Mentor use the cloud in developing EDA tools and running regression testing?

A: Yes, we are users of Azure internally too.

Summary

One classic way to approach a large, compute intensive challenge like SPICE circuit simulation is to divide and conquer, and Mentor’s use of Microsoft Azure to scale up to 10,000 cores for Eldo and AFS tools sure looks like a smarter way to go, compared to building up an internal compute farm.

EDA tools started out with mainframe computers, the early progenitor of cloud-computing, and now with vendors like Microsoft we’ve returned to centralized computing again because it makes sense for peak EDA tool run requirements.

Related Blogs

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Webinar – 3D NAND Memory Cell Optimization

Webinar – 3D NAND Memory Cell Optimization
by admin on 11-07-2019 at 10:00 am
Categories: EDA, Events

Flash memory has become ubiquitous, so much so that it is easy to forget what life before it was like. Large scale non-volatile storage was limited spinning disks, which were bulky, power hungry and unreliable. With NAND Flash, we have become used to carrying many gigabytes around with us all the time in the form of cell phones, USB drives, camera SD cards, even laptops. NAND Flash has been a key enabler for dozens of devices that we use on a daily basis. Because they work so well, they have become taken for granted. In one respect this is a good thing, the best technology is that which blends into our lives and does not stand out glaringly.

Yet, the design of 3D NAND devices is complex and requires a great deal of care and consideration. Designers of 3D NAND memories struggle to balance competing requirements in the design of the memory cells. One area that is particularly interesting is the design of the select gate transistor. When optimized properly it is able to drive the bit in question but will not affect adjacent bits.

Silvaco is planning a webinar on November 21st at 10AM PST that will cover the challenges found in designing optimized 3D NAND. Silvaco will present the usage of TCAD process and device software for optimizing the operation of a 3D NAND memory cell with a focus on the select gate transistor. The end result will be a simulation of the 3D NAND cell operation that includes read/program, erase and program disturb error.

The presenter will be Dr Jin Cho, Principal Application Engineer at Silvaco. Prior to joining Silvaco he has over 15 years of experience in process/device management, including 14/10nm logic technology development. He also has managed a TCAD group for future device development technology. He holds a PhD. From Stanford University.

This technically oriented webinar will thoroughly explore the specifics of 3D NAND design and should be extremely informative. Registration and more details about the webinar are available on the Silvaco website.

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Rapid growth of AI/ML based systems requires memory and interconnect IP

Rapid growth of AI/ML based systems requires memory and interconnect IP
by admin on 11-07-2019 at 6:00 am
Categories: AI, Automotive, Events

Artificial intelligence and machine learning (AI/ML) are working their way into a surprising number of areas. Probably the one you think of first is autonomous driving, but we are seeing a rapidly growing number of other applications as time goes on. Among these are networking, sensor fusion, manufacturing, data mining, numerical optimization, and many others. AI/ML is needed in the cloud, fog and edge. According to Silvaco in a recent webinar, the AI/ML market is going to expand dramatically over the next 5 or 10 years. This should come as no surprise, but the projections are impressive

According to Silvaco there three mega trends driving the semiconductor market. The Smart Cities segment could be worth $1.4B by 2020. Smart City devices themselves will grow from $115M back in 2015 to $1.2B in 2025. The TAM for automotive semiconductors will reach $388B this year. The CAGR for the autonomous vehicle market is expected to be over 41% between now and 2023. For AI, with companies like Apple, Facebook, Google and Amazon designing their own AI chips, the market could easily reach $31B by 2025.

Since the term artificial intelligence was coined in 1956, up until a few years ago, it was characterized largely as an academic field of research. However, with the confluence of a number of key advances, AI/ML has taken off with astonishing speed. Silvaco’s Ahmad Mazumder, the presenter in the Silvaco webinar entitled “AI and Machine Learning SoCs – Memory and Interconnect IP Perspectives” talks about the main enablers for this rapid growth. He cites a number of silicon process technology developments such as strained silicon, high-K metal gate, FinFETs, and EUV lithography as contributing to this growth. The trend will be further accelerated by upcoming developments such as the GAA transistor.

Ahmad also brings up the issue of AI’s accelerated performance growth rate, in terms of GFLOPS, compared to CPUs and GPUs. Neural processing units (NPUs) offer scalability that goes beyond what other processors can achieve. As a result, there are an increasing number of AI/ML based SoCs that are going to be used in every type of computing environment. However, developing these SoCs requires addressing three major challenges: specialized processing, optimized memory and real-time interfaces for connections on and off chip.

AI/ML relies on efficient performance of several specific operations: matrix multiplication, dot products, tensor analysis, etc. Additionally, large bandwidth, high density and low latency memory is necessary for storing intermediate results as they move between processing layers. Finally, fast and reliable interfaces are required for transferring data throughout systems.

Ahmad points out that the growth in AI/ML related SoC development has caused a dramatic uptick in the demand for related IP, like that found in the Silvaco SIPware catalog. They offer IP in many of the essential categories needed for AI/ML based SoC development. The chart below shows Silvaco IP offerings for automated driving (ADAS).

The webinar includes an excellent overview of memory IP, including the JEDEC standards for DDR. We have seen widespread use of GDDR in AI/ML systems, but there are reasons to choose a variety of other types and configurations based on specific system requirements. Ahmad also dives into interface IP and how it plays a significant role in AI/ML systems, and he touches on Silvaco offerings for PCIe and SerDes. They offer IP for PCIe Gen4 and 56G PAM-4 PHY as part of their catalog.

The webinar drives home that point that AI/ML is becoming a major player in almost every kind of computational system, and in order to build hardware that fulfills its promise a wide range of IP needs to be readily available. The full webinar is available on the Silvaco website.

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Calibre Commences Cloud Computing

Calibre Commences Cloud Computing
by Tom Simon on 11-06-2019 at 10:00 am
Categories: EDA, Siemens EDA, TSMC

Calibre was a big game changer for DRC users when it first came out. Its hierarchical approach dramatically shortened runtimes with the same accuracy as other existing, but slower, flat tools. However, one unsung part of this story was that getting Calibre up and running required minimal effort for users. Two things are required for people to change what they are doing and adopt a new approach. The advantages of making the change must be extremely compelling. And, the effort required to make the change must be minimized so that it is not difficult or problematic. Otherwise, people will gladly just keep on doing what they are used to. Mentor knew this then and they apparently still are keenly aware of it now.

Calibre in the Cloud is what Mentor calls their recent announcement regarding running Calibre in a cloud environment. In a technical brief written by Omar El-Sewefy, they discuss several advantages of running in a cloud environment. The main and obvious advantage is scalability. Cloud server offerings usually have the ability to scale up to impressively large numbers of processors. With this scalability comes the potential for higher throughput and the ability to handle peak loads without having to build massive infrastructure in-house. For many organizations DRC checks are infrequent but represent demanding loads on server resources, making cloud computing an attractive option.

However, users do not want to spend excessive time to configure and set up for cloud usage. Mentor laid the foundation for Calibre in the Cloud back in 2006 when they introduced Calibre hyper-remote capability. This let users run on very large numbers of processors to get a significant performance and capacity boost. The process for running in the cloud is very similar to a non-cloud run, minimizing the effort required to set up and run.

The technical brief covers three topics that make cloud runs fast and efficient. They have worked closely with foundries to make sure that the most recent rule decks make the best use of Calibre’s advanced features. As a result, even with increasing rule complexity and data set size, runtimes and memory utilization have remained steady or decreased.

Transporting the data to the cloud is optimized by moving the cells individually, not the flattened design, in what Mentor calls a hierarchical filing methodology. Of course, Calibre needs to assemble the entire design in order to work on it in the cloud. This step is called hierarchical construction mode, where the hierarchical data base (HDB) is created. In prior versions of Calibre, they would allocate and start the worker processes and have them wait for the HDB construction step. In a cloud environment it is more efficient to allocate processes when they are needed. So, one of the key changes in Calibre is called MTFlex, which optimizes CPU utilization so idle processors are not running when they are not needed.

Calibre in the Cloud uses regular licenses so there are no complications from that perspective. Also results and reports can be brought back for viewing in the same way as local runs. Overall Mentor has endeavored to make the entire operation as efficient and smooth as possible. Users can run locally if they want, and then quickly transition to the cloud when production load warrants it.

The technical brief entitled Calibre in the Cloud: Unlocking Massive Scaling and Cost Efficiencies is pretty interesting reading, and makes the point that close collaboration between customers, foundries, cloud providers and Mentor was necessary to deliver a robust solution for scaling by moving to the cloud. Also, at the TSMC OIP Forum in Santa Clara recently Mentor, Microsoft, TSMC and AMD jointly presented the results of using Calibre in the Cloud on a 500M gate design. The presentation on this case study is viewable on demand.

Interestingly running Calibre in the cloud can be an effective solution for large or small companies. Each has their own obstacles to running in periods of peak resource needs. The technical brief can be downloaded from the Mentor website for a full reading.

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ReRAM Revisited

ReRAM Revisited
by Bernard Murphy on 11-06-2019 at 6:00 am
Categories: AI, IP
6 Comments

Memory

I met with Sylvain Dubois (VP BizDev and Marketing of Crossbar) at TechCon to get an update on his views on ReRAM technology. I’m really not a semiconductor process guy so I’m sure I’m slower than the experts to revelations in this area. But I do care about applications so I hope I can add an app spin on the topic, also Sylvain’s views on differentiation from Intel Optane and Micron 3D XPoint ReRAM products (in answer to a question I get periodically from Arthur Hanson, a regular reader).

I’ll start with what I thought was the target for this technology and why apparently that was wrong. This is non-volatile memory, so the quick conclusion is that it must compete with flash. ReRAM has some advantages over flash in not requiring a whole block or page be rewritten on a single word update. Flash memories require bulk rewrite and should therefore wear out faster than ReRAM memories which can be rewritten at the bit-level. ReRAM should also deliver predictable latency in updates, since they don’t need the periodic garbage collection required for flash. Sounds like a no-brainer, but the people who know say that memory trends always follow whoever can drive the price lowest. Flash has been around for a long time; ReRAM has a very tough hill to climb to become a competitive replacement in that market.

Given this, where does Sylvain see ReRAM playing today? The short answer is embedded very high bandwidth memory, sitting right on top of an application die – no need for a separate HBM stack. He made the following points:

  • First, flash can’t do this; this is barely at 28nm today whereas applications are already at much lower nodes. ReRAM is a BEOL addition and is already proven at 12nm
  • (My speculation) I wonder if this might be interesting to crossover MCUs which have been ditching flash for performance and cost reasons. Perhaps ReRAM could make non-volatile memory interesting again for these applications?
  • Power should be much more attractive than SRAM since ReRAM has no leakage current

These characteristics should be attractive for near-memory compute in AI applications. AI functions like object recognition are very memory intensive, yet want to maintain highest performance and lowest power, both in datacenters and at the edge. Even at the edge it is becoming more common to support updating memory intensive training, such as adding a new face to recognize on checking in at a lobby. Requirements like this are pushing to embedding more memory at the processing element level (inside the accelerator), and having HBM buffers connected directly to those accelerators for bulk working storage. Both needs could be met through ReRAM on top of the accelerator, able to connect at very high data rates (50GB/sec) directly to processing elements or tiles where needed.

A different application is in data centers as a high-density alternative to DRAM, as sort of a pre-storage cache between disk/SSD and the compute engine. In this case ReRAM layers would be stacked in a memory-only device. Apparently this could work well where data is predominantly read rather than written. Cost should be attractive – where DRAM runs $5-6/GB, ReRAM could be more like $1. Which bring me back to Intel and Micron. Both deliver chips, not IP so this should be in their sweet spot. I suspect the earlier comment about size and price winning in memory will be significant here. ReRAM may succeed as a pre-storage cache, but it will most likely be from one of the big suppliers.

Another AI-related application Sylvain mentioned which is especially helped by the Crossbar solution is massive search across multi-model datasets. We tend to think of recognition of single factors – a face, a cat, a street sign – but in many cases a multi-factor identification may be more reliable – recognizing a car type plus a license plate plus the face of the driver for example. This can be very efficient if the factors can be searched in parallel, possible with the Crossbar solution which allows for accessing 8k bits at a time.

Particularly for embedded applications with AI, I think Crossbar should have a fighting chance. Neither Intel nor Micron are interested in being in the IP business and neither are likely to become the dominant players in AI solutions, simply because there are just too many solutions out there for anyone to dominate at least in the near-term. Crossbar will have to compete with HBM (GDDR6 at lower price-points), but if they can show enough performance and power advantage, they should have a shot. Consumers for these solutions have very deep pockets and are likely to adopt (or acquire) whatever will give them an edge.

You can learn more about Crossbar HERE.

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Cadence Dives Deeper at Linley Fall Processor Conference

Cadence Dives Deeper at Linley Fall Processor Conference
by Randy Smith on 11-05-2019 at 10:00 am
Categories: Cadence, Events, IP

I wrote about Cadence AI IP not long ago when I covered the Cadence Automotive Summit at the end of July (Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving, Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear). One of those two blogs remains one of my most widely read blogs. In those blogs I spoke quite a bit about the Tensilica DNA 100 processor. Since that event was targeting automotive topics, the focus was of course on delivering advanced automotive features, such as ADAS. At the Linley Processor Conferences, the context is different as the emphasis is on processors. So rather than simply just talking about what is needed for automotive features, Cadence went deeper into the system architecture options that are delivering these solutions using DNA 100, which can apply to far more than automotive. Lazaar Louis, Cadence’s Senior Director of Product Management, Marketing and Business Development for Tensilica IP, did a great job as a presenter, including a short Q&A session.

For AI edge inference, Cadence has three different types of processor IP. Users can choose the best solution for the specific workflow they are planning to use for each problem. This approach makes sense in automotive, where there are many different subsystems. It also makes sense when simply building a consumer IoT product where you want the correct processor for your price point and power budget. The Tensilica HiFi DSP product line is for audio, voice, speech, and AI applications. The Tensilica Vision DSP product line (including the recent Vision Q7 DSP) is for embedded vision processing, imaging, and AI. This year Cadence released the Tensilica DNA 100 as a standalone AI processor. With the increase in AI processing in consumer and automotive products, customers are implementing multi-core solutions with HiFi, Vision and DNA processor IPs to serve audio, vision and AI applications.

I cannot get into all the technical breadth of the Cadence-Linley presentation in this blog. If you want to see architectural details, I believe you can request a copy of the presentation through the Linley website, or simply contact your Cadence sales rep for more information. Lazaar’s presentation featured lots of details related to sparse computing, using a specialized neural network (NN) engine, scalability, high MAC utilization, using the Tensilica Neural Network Compiler, neural network libraries, minimizing accuracy loss due to quantization, and even more. It is rich and in-depth.

What I do want to remind you about is the need for a significant ecosystem. Software plays a large role in all AI/ML solutions. Beyond that you may need different types of semiconductor IP. Cadence is also part of Glow, Facebook’s community-driven approach to AI. Glow is a machine learning compiler for heterogeneous hardware. Cadence has committed to offering processor IP supporting Glow.

In August, I had focused more on the ecosystem around audio solutions as part of Cadence’s infotainment solutions. The list of partners in the embedded vision space is also impressive. Cadence highlighted eight of those partners at the conference, ArcSoft, MulticoreWare, Seemmo, Sensory, Visidon, Morpho, Almalence, and Irida Labs. These solutions can all be combined with Tensilica IP to make some truly amazing results.

Cadence is certainly “focused” (pun intended) on embedded vision. Cadence gave three presentations at the 2019 Embedded Vision Conference: Frank Brill, Portable Performance via the OpenVX Computer Vision Library: Case Studies; Pulin Desai, Highly Efficient, Scalable Vision and AI Processors IP for the Edge; and Shrinivas Gadkari, Fundamentals of Monocular SLAM. It will be interesting to see how cadence continues its effort in embedded vision in 2020.

On a final note, the Tensilica team has been supporting automotive standards for a long time. Rest assured that they have a handle on ISO 26262, ASIL levels, and everything related to automotive safety and reliability. What I pointed to in August, saw again at the AI Hardware Summit in September, at ARM TechCon in October, and at every technical conference I attend, there is one prevailing thought about AI/ML systems – “There is no safety without security.” Cadence’s partnership with Green Hills in this area is to be commended. Security will keep all this dream technology functioning without interference.

This is my final blog of three blogs from the Linley Fall Processor Conference for 2019. The first two blogs are here and here. If processors are your thing, or you just like staying current on the topic, you should consider going to the spring conference. Details are not yet announced, but you should be able to find them here once they are available.

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KLAC- Very Strong Sept & Guide-Foundry up 50%- 5NM & EUV drivers- Outperforming

KLAC- Very Strong Sept & Guide-Foundry up 50%- 5NM & EUV drivers- Outperforming
by Robert Maire on 11-05-2019 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services

  • KLAC Strong Beat on Both Sept Q & Dec Guide
  • Foundry/logic (TSMC) up 50% H2 vs H1
  • Gen 5 acceptance and 5NM rollout drive future

Strong beat in Sept results and Dec Guide
KLAC reported revenue of $1.41B and EPS of $2.48 handily beating street estimates of $1.5B and $2.20 in EPS. More importantly the company guided December to be revenues between $1.425B to $1.515B ($1.475B midpoint) and EPS between $2.39 and $2.69 ($2.54 midpoint), substantially higher than street estimates of $1.39B and $2.35.

The company also upped its estimate of WFE spend in calendar 2019 as the second half of the year has obviously turned out way better than the first half.

Foundry/Logic up 50% H2 versus H1
As we had suggested in our preview, the biggest uptick in business is Foundry/logic which is primarily TSMC spending a lot of money. Even Intel doesn’t come close. Memory remains weak and shrinking versus foundry/logic as a percentage of KLA’s business.

KLA’s core remains very strong
The orbotech acquisition hid the strength of the core KLA business which was up 16% sequentially while the Orbotech business was down slightly for a total 12% sequential growth which in our view is very strong considering that memory is still soft. Obviously this is a very strong annualized rate.

Reticle Inspection outperforming
Wafer inspection was up 13% sequentially but “patterning ” (reticle inspection) was up a whopping 31% sequentially which we attribute to some competitive wins mainly against Japanese competition.

Taiwan (TSMC) led the way with 27% of business with China at 24% , Korea (memory) a low 14% …even Japan was bigger at 15%, US was 13% (Intel).

2020 should be a very good year
The spend by TSMC on 5NM looks to be very large going into 2020. One reason we would cite is that there is little to no equipment reuse from 7NM to 5NM that we expect, so spending on 5NM by TSMC and 7NM by Intel will be for a lot of new equipment. We would also expect some sort of at least partial pick up in memory some time in 2020.

EUV transition pays dividends to KLA
As TSMC transitions from a few layers using EUV to most critical layers using EUV we will not only see a significant jump in EUV scanners, which obviously benefits ASML, but also a corresponding increase in KLA tools to support EUV.

This 4X to 5X increase in the number of EUV layers requires a lot of tools.
Intel, which has not put EUV into production will transition to EUV and will follow a similar tool and spending path as TSMC before it.

Industry Outperform
As we had previewed, its clear that KLA will outperform the growth of the overall semi equipment industry as they have historically been most closely tied to the fortunes of Foundry/Logic which is clearly as strong as memory was two years ago, perhaps even more so.

We think that Foundry/Logic leads memory spending over the next 3 to 4 quarters at least, as we still don’t have a solid idea as to the timing of a memory recovery. This suggests that KLA should keep up the industry outperforman as well given its tie to Foundry/Logic.

The Stock
We would continue to be a buyer of KLAC given the strong report coupled with excellent financials and value returns to shareholders which form a complete picture of an attractive value. Dividends and returns to shareholders continue their 15% trajectory with strong free cash flow and gross margins which continue to lead the industry by a very wide margin. We would view KLAC as our top large cap pick in the space.

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Achronix Announces New Accelerator Card at Linley Fall Processor Conference – VectorPath

Achronix Announces New Accelerator Card at Linley Fall Processor Conference – VectorPath
by Randy Smith on 11-04-2019 at 10:00 am
Categories: Achronix, eFPGA, Events, FPGA

This blog is my second blog from this year’s Linley Fall Processor Conference. The first two blogs focused on edge inference solutions. Achronix’s discussion was much broader than just AI/ML; it was about where FPGA’s have been going and culminated with a product announcement preview. I’ll get to the announcement in a moment, but first, let’s review the growth in FPGA and the markets it serves based on what Manoj Roge, Achronix VP of Product Planning & Business Development presented at the conference.

FPGA 1.0 was the first broad adoption of FPGA technology. The largest usage of FPGA technology was initially in “glue logic,” which is logic used to integrated various components into a system, last-minute adjustments to systems, and programmable IOs. The usage of FPGA technology grew dramatically from the mid-1990s until around 2017. FPGA 2.0 supported more complex functions than FPGA 1.0. For example, in EDA, we saw the growing use of FPGAs in prototyping, verification, and emulation. From FPGA 1.0 to 2.0, TAM (Total Available Market) grew from about $1B to $5B. But now FPGA technology is exploding as the number of growth areas is picking up dramatically. In the past year we have seen FPGA technology projected as an important piece of solutions in several areas including, data centers, edge compute, 5G infrastructure, and automotive, especially ADAS. Manoj implied we could see up to a 6x growth in FPGA TAM between 2018 and 2024.

Achronix is has been furthering the growth in FPGA usage by making the technology available in multiple forms. Achronix has made its FPGA technology available in chip form (Speedster7t), as IP for use as embedded FPGA (called eFPGA) in its Speedcore and as chiplets with its Speedchip FPGA Chiplets. That is many ways to access some very high-performance FPGA technology. Achronix didn’t simply rely on PPA (performance, power, and area) benefits of 7nm FinFET technology, but took a clean slate approach and did a grounds-up design to address the bottlenecks of traditional FPGAs. With Speedster7t, Achronix has reinvented high-performance FPGAs with three key pillars of architecture optimizations – making the compute efficient for Machine Learning Inference, designing the right memory hierarchy, and bandwidth and by efficiently transferring data between compute and memory through true two-dimensional Network on Chip (NoC).

At the conference, Achronix also mentioned VectorPath. This information was a bit surprising since VectorPath was not yet formally announced, but the press release did pop on October 29, 2019. The VectorPath™ S7t-VG6 accelerator card was part of a joint project between Achronix and BittWare, a Molex company. The VectorPath accelerator card will deliver high-performance and high bandwidth at dizzying levels for an FPGA. Pricing was not mentioned, but availability is expected at the beginning of Q2 2020. Features include:

  • 400GbE QSFP-DD and 200GbE QSFP56 interfaces
  • Eight banks of GDDR6 memory delivering 4 Tbps aggregate bandwidth
  • One bank of DDR4 running at 2666MHz with ECC
  • PCIe compliance and certification
  • 20 Tbps 2D NoC inside the Speedster7t FPGA
  • 692K 6-input LUTs
  • 40K Int8 MACs that deliver >80 TOPs
  • OCuLink – 4-lane PCIe Gen 4 connector for connecting expansion cards

There are some interesting choices here. The high-speed interfaces are what data centers are looking for now as they moved forward with 400GbE deployments. Card features have been thought through well so that enterprise-class customers can deploy confidently and future proof their designs with lot of application flexibility. It has been designed for both evaluation and high-volume production applications with the ability to even get this pre-integrated into a Dell or HPE server platform, speeding time to market.

Both GDDR and DDR4 are included, though I think it is the availability of GDDR6 memory support that is critical for highest-speed applications. As you see above, there is even more, but I am sure you get the point that this is seriously fast.

The Speedster7t FPGA family features a 2D network-on-chip (NoC) with more than 20 Tbps bandwidth capacity to efficiently move the data within the FPGA fabric and between the highspeed IOs and the FPGA fabric. The NoC supports AXI channels, so you are still using an industry-standard interface.

To use an FPGA, you need design tools. All the Achronix products mentioned above can be programmed using the ACE  design software, which is included with the purchase of a VectorPath card. ACE handles IP configuration, place & route, timing analysis, bitstream generation/download, and in-system debugging. The synthesis technology is Synplify-Pro from Synopsys though you get it through Achronix. The VectorPath product also comes with a comprehensive board management controller, OS support (Linux or Windows), API, drivers, application examples, and diagnostic self-test. The ability to use the same FPGA code (RTL) and tools across all these FPGA products is a nice feature to have. You could develop code on an accelerator card, reuse parts of it in chiplets, or elsewhere – truly reusable IP, and it is your IP.

I have one more blog coming from the Linley Fall Processor Conference for 2019. If you are into processors, you should consider going to the spring conference. I don’t think the details are announced yet, but you should be able to find them here once they are available. The leading edge is showing up at this event.

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Intel CEO Update Q4 2019

Intel CEO Update Q4 2019
by Daniel Nenni on 11-04-2019 at 6:00 am
Categories: Events, Foundries, Intel Foundry
5 Comments

Bob Swan started as interim CEO in June of 2018 and took the full-time CEO job in January of 2019. I was a vocal critic of the previous CEO Brian Krzanich (BK) and really felt he was not fit to serve. As it turns out I was right. It is not just the CEO himself, but also the people that he surrounds himself with. BK surrounded himself with the Intel old guard and a couple of questionable newcomers, the rest is history.

I do have to thank BK as he is one of the reasons why I am somewhat famous or infamous. We had a very public feud back in the dark days of Intel 14nm and 10nm.

While I am not a fan of CFOs (followers) who become CEOs (leaders) I have high hopes for Bob Swan and the people with whom he will surround himself.

If you take a look at the Intel executive staff today there have been quite a few changes, most notably the addition of Jim Keller as senior vice president in the Technology, Systems Architecture and Client Group (TSCG) and general manager of the Silicon Engineering Group (SEG). Jim is responsible for “architecting the silicon engineering organization within TSCG”. This is a seriously disruptive move on the part of Intel.

For those of you who have not heard of Jim here is his career path graphic:

Jim is mentioned in our book “Mobile Unleashed” in the Apple chapter by the way. PA SEMI figured prominently in the success of the Apple SoC efforts. Jim really is a Silicon Valley legend amongst us semiconductor soldiers in the SoC trenches.

To get a better understanding of Jim Keller take a look at his recent Youtube video he did entitled Jim Keller: Moore’s Law is Not Dead:

It is a full hour but well worth your time, especially if you are one of the ill-informed who think Moore’s Law is dead.

Back to Bob Swan and 10nm, 7nm, 5nm, and 3nm. In the recent conference call Bob mentioned that Intel will get back to the Tick-Tock two year cadence where Tick is a new process and Tock is a new product architecture. Here are some cut/pasted comments from Bob:

The Intel 10-nanometer product era has begun and our new 10th Gen Core Ice Lake processors are leading the way. In Q3, we also shipped our first 10-nanometer Agilex FPGAs. And in 2020, we’ll continue to expand our 10-nanometer portfolio with exciting new products including an AI Inference Accelerator, 5G base station SoC, Xeon CPUs for server storage and network and a discrete GPU. This quarter we’ve achieved power on exit for our first discrete GPU DG1 an important milestone.

We are on track to launch our first 7-nanometer based products, a data center focused discrete GPU in 2021 two years after the launch of 10-nanometer. We are also well down the engineering path on 5-nanometer.

Back in our Analyst Day, we tried to go through this in quite a bit of detail, both, one, kind of our lessons learned coming out of the challenges we had with 10 and how we’re capturing those lessons learned as we think about the next two generations. But first our focus and energy is right now around scaling 10.

And, as we said, we feel very good about the capacity we put in place, the products we have coming down the pipeline and the yields that we’re achieving, almost week-on-week improvement over the last six months. So for 10, we feel really good.

Second, when we put the design rules in for 7-nanometer, we were less aggressive in terms of density. Our learning from going from 14 to 10 is with a benefit of hindsight, we were just — we tried to scale at a 2.7 factor and that was — that ended up putting too much invention or revolutionary nodes into the fab environment to meet those kind of hurdles and the learning from that is, we just can’t hit those kind of really aggressive targets, when, to your point, the dynamics are getting increasingly challenging. So lots of learnings out of 10. Our transition to 10 that we incorporated into 7, the design the design rules there’s less complexity and for the last couple of years that we’ve been working with EUV.

Litho has been the challenge. We’ve had EUV that we’ve been working with for a few years now and we expect to use EUV as we scale 7. And we indicated that our first product will be two years from this quarter. So fourth quarter of 2021, our first 7-nanometer product will come out and our expectation is that we’ll get back on a two-year cadence from 7 and beyond. So lots of learning out of 10-nanometer that we’ve incorporated, and we said back in May and we reiterated today, we expect to be back to a two to two-and-a-half year cadence going forward at least for the next few nodes.

Bottom Line: Intel got too aggressive at 10nm with 2.7x scaling without EUV and the design rules were much too complex for the process maturity. Intel 10nm is finally in HVM after a four year delay and 7nm is well under way. EUV is in HVM at TSMC, TSMC did the heavy EUV lifting, so I have confidence Intel will get 7nm in 2H 2021, hopefully.

Intel 7nm will be FinFETs (yawn) but Intel 5nm will be horizontal nanosheets and Intel 3nm CFETs. Interesting times ahead at Intel, absolutely!

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