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The IoT will meet 5G soon, but not with the old SIM cards

The IoT will meet 5G soon, but not with the old SIM cards
by Tom Simon on 05-16-2019 at 7:00 am
Categories: 5G, IoT, IP, Mobile, Synopsys

By now you have probably realized that 5G is a lot more than an incremental change from previous 3G and 4G cellular technology. For instance, 5G will be used to connect our phones in completely new ways, such as with microcells in urban areas using mm-wavelength signals. 5G will also include two low power protocols that are intended for use by IoT devices. One is Narrowband IoT (NB-IoT), which is intended for indoor use, with low power and long battery life. The other is LTE-M, which has a higher data rate and range than NB-IoT. However, it is still intended for machine to machine (M2M) links. GSA reports that as of March 2019 104 operators in 53 countries have already deployed or launched one or both of NB-IoT or LTE-M technologies.

While they may be different than the protocols used for voice handsets, NB-IoT and LTE-M will share the high security offered by SIM (subscriber identification module) technology. Many of today’s IoT devices are now living in a wild west type of security environment. Understandably, the move to a robust identification will be welcome indeed.

SIM conjures up images of those hardware modules that are inserted into our phones to enable devices to work on carrier networks. Today cell phone and mobile hot spot users need to fumble with SIM cards when it comes time to switch carriers, or devices. Inserting and removing SIM cards might be fine for the devices we keep on our person, but IoT deployments often consist of many devices, which might be far flung and/or difficult to access. Simply put, swapping SIM cards is a non-starter for IoT deployments in the future.

A SIM card is not just a machine-readable serial number. It’s an application running on a processor and storage in the card itself. The physical card is called a Universal Integrated Circuit Card (UICC). The UICC has storage for user specific information such as a phone book and text messages, in addition to the unique identifier for the wireless customer. Because the UICC is self-contained, it can be securely manufactured to ensure security. In order to replace the SIM card with something embedded in the connected device, remote provisioning protocols were developed by the GSMA. This new embedded UICC is called eSIM or eUICC and is frequently a small chip that is soldered into the IoT or mobile device when it is manufactured. However, this still adds to the BOM, requires extra steps in manufacturing and takes up precious space in the device.

The next step in this evolution is a fully integrated UICC, called iSIM, that can be designed right into the device’s SOC. Extra care must be taken to provide a secure execution environment for the iSIM. Synopsys has recently published a write up on their website that goes into the topic of putting together a complete solution for iSIM, including hardware IP, application software and remote provisioning capability. iSIMs can be used with any service provider, but there is still a need for a commercial solution to transfer Profiles for any carrier into the iSIM. Synopsys has partnered with Truphone for this service and has completely integrated the process to eliminate boot strap issues in the field.

Designers can start with Synopsys DesignWare tRoot Fx Hardware Secure Modules (HSMs) and add their own preferred eSIM/eUICC solution, which could be from an internal source, a Synopsys partner or any third party. The Synopsys HSM contains all the hardware modules needed to build a secure working iSIM. Alternatively, Synopsys offers the tRoot V330 HSM for iSIM that is a complete solution.

Reference: Move the IoT from WiFi to Global Cellular – Securely

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56thDAC ClioSoft Excitement

56thDAC ClioSoft Excitement
by Daniel Nenni on 05-15-2019 at 12:00 pm
Categories: Cliosoft, EDA, Events

As the number one 56thDAC supporting portal we will publish what’s happening in the conference, on the exhibit floor, and outside activities. The SemiWiki bloggers will be out in full force with live coverage and behind the scenes looks. Remember, SemiWiki bloggers are actual semiconductor professionals with hundreds of years of combined experience. There is no media team out there that loves DAC more than we do, absolutely.

ClioSoft is also a longtime DAC and SemiWiki supporter and let me tell you ClioSoft CEO Srinath Anantharaman does not spare the DAC expense:

ClioSoft DAC Demo Description

Join us at the 56th Design Automation Conference (DAC) in Las Vegas, NV in booth #927 to learn about our industry standard SoC design and IP management solutions that are tailormade for the semiconductor industry.

 

  • SOS7 platform is the design collaboration system of choice for analog, RF, digital and mixed-signal designs at over 300 companies such as Analog Devices, arm, Cadence, Google, Mediatek and TSMC.
  • designHUB platform, launched two years ago, successfully enables companies in making IP reuse a reality within their enterprise.


Re-using Your IPs To Develop SoCs Faster

  • What internal or 3[SUP]rd[/SUP] party IPs are available for use within the company?
  • How can I search and compare IPs, review their usage and resolve any questions with the IP developers prior to selecting the IP?
  • Can I review the experience of other designers using this IP before using it?
  • How can I track and prevent the unauthorized usage of 3[SUP]rd[/SUP] party IPs?

The designHUB platform empowers you to easily search for IPs across your company, compare the results, review their issues across hierarchies, qualify and select the desired IP for your project. Collaborate with your fellow team members and keep them in-sync during the development phase of your SoC and leverage the existing IP knowledgebase to resolve any IP issues in a timely manner. On completion, publish your SoC or parts of it into the IP repository with the desired access controls. In this demo, you can learn how to track the IPs and their usage throughout your enterprise, set up checks to prevent IP theft and leverage a live and growing knowledge-base for better efficiency.

Managing And Reusing Your Analog IPs Successfully

  • Do you want to browse for IPs from the Cadence Virtuoso platform based on certain criteria such as libraries, process nodes, foundries etc.?
  • Do you want to download a version of an IP into your workspace, make the necessary modifications and publish it, directly from Cadence Virtuoso?
  • Do you want to track the usage of the analog IPs and its variations throughout the company?
  • Do you want receive notifications on changes made to the IPs used in your project?

This demo will explain how to collaborate easily with different teams to develop and publish your analog IPs directly from the Cadence Virtuoso platform by using the designHUB ecosystem. You will learn how to create, manage and reuse the different versions of IPs for specific PDKs and foundries by using the designHUB platform while leveraging a live and growing knowledge base. See how your team can collaborate efficiently on their analog/mixed signal designs and leverage internally developed resources – semiconductor IPs, flows, scripts etc. to build SoCs successfully within a shorter time.

Managing Your Designs For Successful Tapeouts

  • Are you struggling with managing design data from multiple design flows across multiple design centers?
  • Do you find it difficult to manage design handoffs between teams of your project?
  • Are you spending too much time investigating changes made to the design or wondering whether you have the latest version of the design data?
  • Are you blowing up your budget on network storage?

Learn how you can leverage the SOS7 design management platform, already in use by over 300 customers, for collaborating on all analog, RF, digital and mixed-signal designs, to increase their designer productivity and team efficiency. See how SOS7 enables you to manage your designs, track open issues, take snapshots of your design database and provides a non-intrusive way to manage your design handoffs between different teams. Take a look at the different ways SOS7 can keep your data secure and minimize your network storage space used for your project.

Managing Design Traceability For Automotive Electronics

  • Are you looking to identify the design modifications made since yesterday?
  • Do you want to track what design changes were made to fix this bug?
  • Do you want to trace the usage of this IP across your company?
  • Which designs have been implemented using this version of the specification?

Want to learn how you can track documents, IPs, issues and their fixes against the IP/SoC implementation? This is the demo for you. See how to view the open issues hierarchically for the IPs, be notified about the fixes, review what changed and track the usage across different SoC implementations. From a design module perspective, see how you can track the usage across different projects and view open issues associated with it or track the various documents and its revisions used during the implementation as well as the issues found against a requirement.

Visual Design Diff

  • Does your design team struggle to identify modifications made to the schematic or layout by other team members?
  • Are you having problems reviewing the changes in your schematic or layout during ECOs?

Learn to use Visual Design Diff (VDD) to graphically compare different versions of a schematic or layout and to quickly highlight the differences even when the schematic is modified by a RF designer.

About designHUB:
The designHUB platform provides a collaborative IP reuse ecosystem for enterprises. With built-in analytics and collaborative tools, designHUB not only improves IP reuse by providing an easy-to-use workflow for designers to leverage their internal resources but it also enables design teams to collaborate efficiently to develop SoCs faster. Enabling designers to be more productive, designHUB tracks and collates all activities for design projects and displays the notifications and tasks assigned in an easy review dashboard.

About SOS7:
ClioSoft’s SOS7 design-management platform empowers single or multi-site design teams to collaborate efficiently on complex analog, digital, RF and mixed-signal designs from concept to GDSII within a secure design environment. Tight integration with EDA tools, and an emphasis on performance for data transfer, security and disk space optimization provides a cohesive environment that enables design teams to streamline the development of SoCs. SOS7 facilitates easy design handoffs between teams and mitigates the possibility of design re-spins.

About ClioSoft:
ClioSoft is the pioneer and leading developer of enterprise system-on-chip (SoC) design configuration and enterprise IP management solutions for the semiconductor industry. The company provides two unique platforms that enable SoC design management and IP reuse. The SOS7 platform is the only design management solution for multi-site design collaboration for all types of designs – analog, digital, RF and mixed-signal and the designHUB platform provides a collaborative IP reuse ecosystem for enterprises. ClioSoft customers include the top 20 semiconductor companies worldwide. The company is headquartered in Fremont, CA with sales offices and distributors in the United States, United Kingdom, Europe, Israel, India, China, Taiwan, Korea and Japan.

Also Read

A Brief History of IP Management

Three things you should know about designHUB!

Data Management Challenges in Physical Design

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Getting to EMC Compliance by Design

Getting to EMC Compliance by Design
by Bernard Murphy on 05-15-2019 at 7:00 am
Categories: Ansys, Inc., Automotive, EDA

At the risk of highlighting my abundant lack of expertise in the domain, I had always viewed EMC (electromagnetic compatibility) compliance and testing as one of those back-end exercises that can only be done on the real device and depends on a combination of expertise and brute-force in chip/package/module/system design (decaps, etc) to ensure a reasonable chance of passing. One site I found has some interesting stats in this area, suggesting first time pass-rates of only 50%, and rather lax enforcement in practice for non-wireless devices, indicating that getting to compliance is not trivial, nor has it been considered especially important, at least by a significant number of vendors.

However it seems this is likely to change. As devices move into much more safety critical applications, particularly in cars, expectations are rising. Not only is there likely to be a high and more strictly enforced requirement that applications (including non-wireless devices) will not interfere with other external electronics, but also testing for immunity of the device itself to external interference is becoming more sophisticated. The FCC has announced new rules requiring EMC testing to be done only by accredited labs with the resources and equipment to meet these needs, a factor which apparently is driving significant consolidation among labs to get to this new critical mass.

So, more rigorous and more expensive testing, together with more rigorous enforcement and potentially significant fines for non-compliance. In advanced technologies running at higher frequencies, more help to design for compliance will probably be welcome. ANSYS recently hosted a webinar in which Professor Nagata of Kobe University presented the work they are doing, together with Toshiba and ANSYS, to explore methods to design for and simulate for compliance while still at the design stage. Simulation is supported by the ANSYS RedHawk and HFSS among others.

They are particularly looking at effects of interference, both internal and external, in LTE subsystems, for example in V2x applications. Here, noise can come both from internal circuitry, the regular power noise as functions in the chip become active or inactive, as well as the noise from switching power domains that are common in many low-power applications today.

They attack both components of EMC – electromagnetic interference (EMI) generated by the application, and electromagnetic susceptibility (EMS) to external interference – using the ANSYS tools. I am not going to attempt to replay the level of detail Professor Nagata goes into; you can watch the webinar replay for a closer understanding. The main top-level points I saw are that:

  • They use both passive models for the chip, package and system in their response model, and active models for the ESD devices at the chip I/Os. Their comparison of simulations based on this approach with measured response curves show good correspondence, so I’m sold that the methodology is robust.
  • Analysis starts by building EMC awareness at chip design, supported by a reference PCB model. They then iterate from package design and model through IC design based on a chip power model (CPM). The EMI component of this Professor Nagata considers fairly straightforward. He says that EMS analysis is not so easy since this needs to account for non-linearity in the ESD devices in response to potentially Watts of external signal. To deal with this they use an extended CPM model to include the active (non-linear) behavior
  • One the chip model is optimized, they pass this extended CPM model over to the PCB analysis team to support their compliance modeling, again an iterative process to optimize for and effective while managed-cost solution.

Professor Nagata did note that their work is still at the research phase, but it seems quite promising already. Building EMC compliance analysis into the chip, package and system phases of design sounds like a better way to converge on successful certification against these new regulatory requirements. You can register to watch the webinar HERE.

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Achieving a Predictable SignOff in 7nm

Achieving a Predictable SignOff in 7nm
by Alex Tan on 05-14-2019 at 12:00 pm
Categories: Ansys, Inc., EDA, FinFET

Designing with advanced-nodes FinFETs such as 7nm node involves a more complex process than prior nodes. As secondary physical effects are no longer negligible, the traditional margin-based approach applied at various design abstraction levels is considered ineffective. Coupled with the increase of device counts, failing to account for all of these effects will add design risks including impact to yield and PPA (Power, Performance and Area).

Variability and Margin
Without proper analytics, the physical effects generally accounted for as variability in many forms (voltage drop, temperature, process) and its manifestations such as timing uncertainties, margin, derating, etc., pose significant challenges to the design closure. The grid complexity in 7nm designs (with power grids in the order of 10B+ nodes) has increased and the use of ultra-low voltage supply has also compressed margin and worsened variability, demanding an increase in scenario coverage to ensure voltage and timing closures.
Furthermore, the variability increase also complicates predicting true silicon behavior, which is critically needed for a successful product ramp process.

In the Ansys Webinar titled “Addressing Multiphysics Challenges in 7nm FinFET Designs”, a holistic approach in addressing these challenges was presented. It started with the understanding of how the design fits within the process space and what types of subjected scenarios that could lead to potential design risks.

Power Integrity and Thermal
At the epicenter of these challenges is power, a critical source to each device operation on the silicon. Power distribution network (PDN) integrity drives switching activities and is prone to imbalances that could induce undesired surprises such as IR drop issues. For example, poor bump and RDL design could contribute to poor on-chip device operation or even failure at silicon bring-up.

As expected, the initial objective is to identify potential hotspot localities and fix these vulnerabilities early during the design implementation cycle. Consequently, an accurate way of quantifying the interacting physics is needed. For example, the analytics tool such as Ansys’ RedHawk helps identify an IR drop caused by packaging or design activity, and provide data points for corrective remedies.

In a wider context, assessing power integrity in the design flow starts at the power planning stage, in which grid quality is analyzed through BQM (Build Quality Metrics) approach. During the subsequent block-level build and PDN optimization, multiple reliability analysis such as static/dynamic voltage drops and signal EM (EMIR) are done. Structural grid checks are then applied to locate potential issues. Given that it is easier to put out a fire on a few trees than fighting a forest fire, fixing localized design issues early helps to contain smaller problems from getting out-of-hand. For example, taking care of the outliers in the generated histogram from analytics data can reduce the number of critical issues into a manageable list.

Aside from power, thermal is also another critical factor. The heat generation, dissipation flow and thermal couplings of chip components versus any optical components in a heterogeneous 3D-IC could impact the overall chip power or performance. Localized activities and PVT conditions also influence the device aging process.

Multivariable and Predictive Signoff
The key to tackling multiphysics challenges is to infuse analytics into the existing solution such as in power integrity methodology in such as a way that it enables a predictive signoff quality. The traditional analysis flow utilizing both vector and vectorless simulation approach has challenges, as it relies on a set of correct scenarios selection. For example, many modern designs have application dependencies that may uniquely translate to different activities sequences at the core level. Therefore, to arrive at a set of vectors that provide good coverage of activities is hard.
As the impact of multiphysics interactions are eventually measured in term of performance design metric (timing), it is necessary to facilitate feeding back the various simulation generated data points into the overall design closure flow. Ansys’ Path FX platform fills the gap between SPICE level circuit simulation and static timing analysis. It provides context-aware multiphysics timing analysis and complements the mainstream design flows by retaining the performance, capacity and usability of timing analysis engine.

Path FX target use models include to complement existing STA by validating at risk paths at each design iteration, identify safe slack and add additional guardband to at-risk paths not covered by margins. It is also capable of fine-tuning the process models for better correlation with silicon and use them to further identify at-risk paths. On a 7nm testcase, it delivers an accuracy within 2% versus SPICE simulation result. Path-FX has also been integrated with RedHawk-SC to address voltage drop impact assessment on timing. With Ansys’ SeaScape architecture it enables design teams to leverage big data analytics to handle the data demands of multiphysics chip-package-board simulation and testing.

In summary, 7nm designs are subject to a more complex multi-physics environment. Successful silicon tapeout and bring up require addressing their impacts on delay variability, validating at-risk areas on silicon and proper use of safe guardband.

To view this on-demand Webinar on how Ansys multiphysics simulations can address the different forms of variability and their impact on performance, please check HERE.

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Trade war shifts electronics production

Trade war shifts electronics production
by Bill Jewell on 05-14-2019 at 7:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

The U.S. is showing steady growth in electronics production. Three-month-average change versus a year ago (3/12) in March 2019 was 6.2%, the 12[SUP]th[/SUP] consecutive month of growth above 5%. China electronics production is decelerating, with March 2019 3/12 growth of 8.2%, similar to 8.3% in February. This marks the first time China electronics production growth has slowed below 10% since November 2016. The 28 countries of the European Union (EU) displayed a decline in 3/12 electronic production in December 2018 through February 2019 following volatile but mostly positive growth the prior two years.

Electronics production in key Asian countries is also a mixed picture. Taiwan now has the highest growth in the region, with March 2019 3/12 growth of 15%, the third consecutive month of double-digit growth. Taiwan has recovered from production declines in 2015 through 2017. Vietnam’s 3/12 growth slowed to 1% in April 2019 following strong growth over the last two years, hitting over 60% in December 2017. South Korea, Malaysia, Singapore and Japan are all experiencing declines in the last few months. Japan has been weak over the last year, while the other three countries had double-digit growth at some point in 2018.

What impact has the ongoing trade dispute between the U.S. and China had on electronics production? Looking at U.S. imports of electronic equipment in the first quarter of 2019 versus a year ago gives an indication of the trends. Overall U.S. imports of electronic equipment were $58.8 billion in 1Q 2019, down $2 billion or 3.4% from 1Q 2018. Imports from China were down $3.7 billion, or 11%. Imports from Mexico held steady at $10.9 billion. Vietnam has emerged as the third largest source of U.S. electronics imports, with $4.4 billion in 1Q 2019, up $2.2 billion or 95% from a year ago. Taiwan was the fourth largest source, with $2.2 billion, up 45% from a year ago. Thailand and most other countries showed a decline in U.S. electronics imports from a year ago. The steady growth of U.S. electronics production as shown above while imports have declined indicates some possible shift of electronics production back to the U.S.

Four years ago in February 2015 we at Semiconductor Intelligence wrote about the emergence of Vietnam as an electronics manufacturer. The U.S.-China trade dispute has accelerated the growth of Vietnam electronics production. Examples of the shift include:
· In April, LG Electronics announced it would cease production of smartphones in South Korea and shift manufacturing to Vietnam.
· The world’s third largest producer of televisions, China’s TCL, in February began construction of a major TV production facility in Vietnam.
· Key Tronic, a U.S.-based contract manufacturer, expects to shift some production from China to Vietnam with the opening of a new factory in Vietnam in July.

Taiwan has also benefited from the U.S. trade dispute with China. An April Bloomberg article states 40 Taiwanese companies are moving some production back to Taiwan from China, helped by incentives from the Taiwan government. These companies are investing US$6.7 billion and plan to create over 21,000 jobs.

Although the shift of electronics production from China to other Asia countries has been accelerated by the current trade dispute, the trend has been in place over the last few years. Multinational companies are moving production to Vietnam and other countries due to lower labor costs, favorable trade conditions and openness to foreign investment.

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Re Energizing Silicon Innovation

Re Energizing Silicon Innovation
by Bernard Murphy on 05-13-2019 at 12:00 pm
Categories: AI, Automotive, Events, Intrinsix, Prototyping, S2C EDA, Synopsys, TSMC
2 Comments

Hardware is roaring back into prominence in technology innovation, from advanced cars to robots, smart homes and smart cities, 5G communication and the burgeoning electronification of industry, medicine and utilities. While software continues to play a role, all of these capabilities depend fundamentally on advances in hardware and particularly novel chip solutions: in sensing, high performance and/or low power compute and communication, AI accelerators and many more functions. Yet amidst this explosive growth, the semiconductor industry has massively consolidated. Fewer and bigger companies do their part to drive innovation but are naturally more risk-averse and more inclined to evolutionary rather than revolutionary advances. Where’s all the real innovation and risk-taking going to come from in this environment?

Thirty to forty years ago, if you could make a convincing case there were plenty of VCs ready to bankroll your venture. As manufacturing costs for advanced processes grew, VCs found the comparably minor capital needs of software ventures much more attractive and steered away from silicon business plans. But designers didn’t stop having ideas or feeling the itch to start new enterprises; they were just stalled by a seemingly insurmountable barrier to entry – raising seed and Series A funding.

Everyone knew this, but Rick Lazansky wanted to do something about it. Rick is a serial entrepreneur, actively involved in the investment community. He believed the industry needed an incubator to help silicon innovators with good ideas get past this hurdle. Incubators and accelerators are not new concepts but his creation, Silicon Catalyst, makes particular allowance for the special needs of this domain. They provide a pool of seed investors, two years of design tool access, manufacturing and test, access to a wide range of advisors with lots of industry experience and access to a premium group of strategic partners looking for innovations they need. You’ll still have to raise some of your own investment to prove you have skin in the game, but the barrier is now much less daunting.

Before you quit your job, get a second mortgage on the house and tell your significant other that the family will be living with your parents if your venture doesn’t work out, remember that as with any incubator, you’re going to have to do some work to be accepted; I’ll get to that. But first some more detail on that buffet of goodies to which you’ll have access if you cross that hurdle.

Your immediate concern is probably how you manage EDA, IP and design services, MPW, packaging and test costs. Silicon Catalyst has assembled a group of 25+ in-kind partners who will provide 2 years of free or significantly-discounted access to their capabilities and services from the time your clock starts. These include Synopsys for design tools, S2C for emulation, SiFive and Silvaco for IP, TSMC MPWs for prototype manufacturing, Advantest and EAG for test, Mathworks, AWS, Instrinsix, MEMS design and foundry solutions, patent lawyers, even a CFO app – and many more. They cover pretty much everything you’re going to need to create that prototype. These partners see value in this access because they see the portfolio companies as potential new customers.

There are multiple strategic ecosystem partners, including Bosch, On Semiconductor, Soitec and TI Semiconductor; I met the Bosch representative at a recent event. Strategic partners pay close attention to the portfolio companies working in their areas of interest. Bosch knows that that interesting startups have neither bandwidth nor the nerve to approach a company of their size. By being a strategic partner, they can interact with promising ventures very early on during the screening process and react quickly if they see a fit. Others see opportunities in hot areas such as photonics where they see potential to build further demand for their technology.

Among advisors, full disclosure – I’m now an advisor, but they have some really good people too. Just a small sample includes Dave French (past CEO of Cirrus Logic and EVP at NXP), John East (past CEO of Actel Semi), Misha Burich (past CTO and VP at Altera) and Mark Ross, (ex-Cypress Semi EVP & CTO). There are 120+ advisors aligned with Silicon Catalyst, with skills ranging from globalization to manufacturing development, angel investments, MEMS – it’s all on the website.

Investors include Rick himself, Jim Hogan and many of the advisors. There are options for seed money to come from individual investors, also from an ecosystem investor group to which multiple angels can contribute. Angels particularly are attracted by the reduced risk over personal investing. In the personal approach there’s a lot of risk and a lot of work for an investor to decide where and how much they should invest. Investing together with others in in a pre-screened group of portfolio companies can look like a pretty attractive proposition. The Silicon Catalyst approach reduces risk all round – for portfolio startups, investors, in-kind and strategic partners.

Silicon Catalyst looks at opportunities from lots of domains and geographies, spanning pre-seed to post-Series-A chip startups. Existing portfolio companies are in analog-based AI, communications, ultra-low power design and others, some in Silicon Valley but also in Canada, Korea and Singapore. From their founding in 2015, they’ve connected to over 250 startups, receiving applications from Europe, India and other locations. There’s now a joint venture in Chengdu, China focused on the power semiconductor ventures and they’re exploring the possibility of another joint venture to assist startups in Israel.


So what’s the catch? Applicants are screened through a rigorous review process; historically, only one out ten makes it through to becoming a portfolio company. That’s so all those supporting individuals and organizations feel they are getting value for their investments in the domains that most interest them. Nick Kepler (COO) told me that even though selection is obviously rigorous, he wants to make sure that each applicant gets value out of the process even if they aren’t selected. Worth remembering even if you’re not sure you are ready. This could be a way to find out what you have to do to tune up your game.

Silicon Catalyst has around 20 companies in the portfolio, they raised their own investment round last year and they’re planning to get to several hundred companies in the portfolio over the next 7-10 years. As a measure of success, they already have portfolio companies who have graduated from the incubator to Series A funding.

OK, I’m obviously biased. But c’mon – when did you last see an idea this exciting for any would-be silicon entrepreneur? If you want to learn more, first click HERE. Also know that upcoming events for their ecosystem members include a Portfolio Company Update (what others call “Demo Day”) and their Semi Industry Forum, both at the end of May. And for you entrepreneurs, the deadline to apply for the Fall Screening Event is in July. Check out their website to learn about the application process.

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The Evolution of the Extension Implant Part V

The Evolution of the Extension Implant Part V
by Daniel Nenni on 05-13-2019 at 7:00 am
Categories: Events, Semiconductor Services, Threshold Systems
1 Comment

Part 4 of this series discussed how a transistor Extension could be fabricated in a planar device without using an implant operation, and is instead formed using a preferential etch followed by a selective epitaxial deposition. This final installment of the series will present the formation of an Extension in a FinFET transistor using the same etch and deposition methodology.

As in the planar case, this technique for fabricating an Extension region depends on etching out a precisely formed cavity adjacent to, and on both sides of, the transistor channel region. Also, like the planar case, this cavity etch is performed as part of the replacement Source/Drain etch that takes place prior to the epitaxial deposition of the SiGe compressive stressor. However, in the case of a FinFET, the Extension cavity is formed as part of the fin removal process.

Figure #1 illustrates PMOS and NMOS fins just prior to the Source/Drain cavity etch and the formation of the SiGe stressor crystals. The NMOS fins are coated in a protective hard mask. (Note that the PMOS fins are located in the N-Well and the NMOS fins are located in the P-Well.)


Figure #1

The process begins by etching away the PMOS fins located outside of the gate electrode. This is accomplished by first etching away the thin coating of oxide (left on the on the top of the fins after the sidewall spacer etch), and then etching away the Silicon fins using a wet etch of NH[SUB]4[/SUB]OH. Alternate etch chemistries that will also work for this task are NH[SUB]3[/SUB]OH, TMAH, KOH, NaOH, BTMH or amine-based etchants.

Once the fins are removed, the nitride spacers along the fin sidewalls will collapse and they can be easily removed from their attachment points to the Gate Electrode nitride spacer. The result of this etch is illustrated in figure #2.

 

Figure #2

Figure #2 displays the device structure after the PMOS fins have been removed. The TMAH etches preferentially into the N-Well forming the characteristic “V” shaped groove that self-limits the etch process. Perpendicular to this groove, and along the (111) plane, the TMAH etches the silicon fin more slowly and forms the Extension cavity beneath the Gate Electrode spacer. Figure #3 displays a close-up view of the Extension cavity.


Figure #3

Following the etch, a selective deposition of SiGe takes place. This operation will deposit SiGe only on the exposed silicon surfaces which restricts the deposition to the silicon in the V-shaped groove and the Extension cavity as displayed in figure #4.

Figure #4

The Gate Electrode in figure #4 has been made transparent in order to make the Extension structure visible. Figure #5 is a close up of the Extension structure that is located beneath the Gate Electrode spacer.


Figure #5

So is this technique for forming the transistor Extension actually being used?

Figure #6 displays a Transmission Electron Micrograph of an Intel 22nm PMOS FinFET gate array.

The TEM preparation of this image makes it initially difficult to understand. It is a dark-field image so the denser materials appear lighter and the view is top-down and the Gate Electrodes have been polished back to the tops of the SiGe crystals. As a result of this polish, the Gate Electrodes no longer wrap around the top of the fins but are located on either side of them. This reveals the transistor channels and the Extensions located on either side of the channels.

As the TEM illustrates, the SiGe crystals extend behind the nitride spacers and slightly into the channel region to form the transistor Extensions. Based on this evidence it would appear that the technique described in this paper has been in use for some time.

Figure #6

Forming the transistor Extensions as part of the fin removal and SiGe deposition process offers a number of important advantages. First, it is a simpler process. It eliminates all of the implant steps required of other Extension formation methodologies and their associated photo-masking operations. More importantly, it provides a robust solution for effectively forming transistor Extension regions even with the very tight Gate Electrode pitches found at the 10/7/5nm nodes.

This technique would require careful control of the fin removal etch to ensure that the Extension cavity is formed to the correct dimensions, but the advantages provided by this method far outweigh any disadvantages.

This content was authored by Jerry Healey of Threshold Systems Inc. For detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.

Also read: The Evolution of the Extension Implant Part IV

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Uber’s Sandcastle

Uber’s Sandcastle
by Roger C. Lanctot on 05-13-2019 at 7:00 am
Categories: Automotive
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As Uber’s initial public offering arrives this is a good moment to consider what kind of employment model for the future we all, as employees and employers, would prefer to adopt: Amazon or Uber?

One of my sons has interviewed with Amazon. The other has his Amazon moment today. My across-the-street neighbor works for Amazon Web Services. I don’t know anyone that works for or has “interviewed” with Uber – though I have spoken with Uber drivers all over the world.

It is worth considering the two different value propositions posed by these pivotal employers and purported economic engines. Amazon is already the second largest employer in the U.S. with 566,000 employees. Uber employs more than 22,000 people at headquarters or in support roles along with more than three million drivers.

Municipalities and states vie over incentives to entice Amazon to open facilities (headquarters, distribution centers, server farms) in their areas thereby bringing employment. Amazon leverages that local support to demand concessions such as a greening of existing power grids, for example, in the case of server farms installations.
Amazon is famous for its 14 leadership principles:

1. Customer Obsession
Leaders start with the customer and work backwards. They work vigorously to earn and keep customer trust. Although leaders pay attention to competitors, they obsess over customers.

2. Ownership
Leaders are owners. They think long term and don’t sacrifice long-term value for short-term results. They act on behalf of the entire company, beyond just their own team. They never say “that’s not my job.”

3. Invent and Simplify
Leaders expect and require innovation and invention from their teams and always find ways to simplify. They are externally aware, look for new ideas from everywhere, and are not limited by “not invented here”. Because we do new things, we accept that we may be misunderstood for long periods of time.

4. Are Right, A Lot
Leaders are right a lot. They have strong judgement and good instincts. They seek diverse perspectives and work to disconfirm their beliefs.

5. Learn and Be Curious
Leaders are never done learning and always seek to improve themselves. They are curious about new possibilities and act to explore them.

6. Hire and Develop the Best
Leaders raise the performance bar with every hire and promotion. They recognise people with exceptional talent and willingly move them throughout the organisation. Leaders develop leaders and are serious about their role in coaching others. We work on behalf of our people to invent mechanisms for development like Career Choice.

7. Insist on the Highest Standards
Leaders have relentlessly high standards – many people may think these standards are unreasonably high. Leaders are continually raising the bar and driving their teams to deliver high quality products, services and processes. Leaders ensure that defects do not get sent down the line and that problems are fixed so they stay fixed.

8. Think Big
Thinking small is a self-fulfilling prophecy. Leaders create and communicate a bold direction that inspires results. They think differently and look around corners for ways to serve customers.

9. Bias for Action
Speed matters in business. Many decisions and actions are reversible and do not need extensive study. We value calculated risk taking.

10. Frugality
Accomplish more with less. Constraints breed resourcefulness, self-sufficiency and invention. There are no extra points for growing headcount, budget size or fixed expense.

11. Earn Trust
Leaders listen attentively, speak candidly, and treat others respectfully. They are vocally self-critical, even when doing so is awkward or embarrassing. Leaders do not believe their or their team’s body odour smells of perfume. They benchmark themselves and their teams against the best.

12. Dive Deep
Leaders operate at all levels, stay connected to the details, audit frequently, and are sceptical when metrics and anecdote differ. No task is beneath them.

13. Have Backbone; Disagree and Commit
Leaders are obligated to respectfully challenge decisions when they disagree, even when doing so is uncomfortable or exhausting. Leaders have conviction and are tenacious. They do not compromise for the sake of social cohesion. Once a decision is determined, they commit wholly.

14. Deliver Results
Leaders focus on the key inputs for their business and deliver them with the right quality and in a timely fashion. Despite setbacks, they rise to the occasion and never compromise.

These principles serve as the framework for an interview gauntlet known as “having a loop.” It’s a daunting process that not all are able to conclude successfully.

Uber’s CEO, Dara Khosrowshahi, famously reworked Uber’s cultural code when he joined the company:

Uber’s Cultural Norms
We build globally, we live locally.We harness the power and scale of our global operations to deeply connect with the cities, communities, drivers and riders that we serve, every day.

We are customer obsessed. We work tirelessly to earn our customers’ trust and business by solving their problems, maximizing their earnings or lowering their costs. We surprise and delight them. We make short-term sacrifices for a lifetime of loyalty.

We celebrate differences. We stand apart from the average. We ensure people of diverse backgrounds feel welcome. We encourage different opinions and approaches to be heard, and then we come together and build.
We do the right thing. Period.

We act like owners. We seek out problems and we solve them. We help each other and those who matter to us. We have a bias for action and accountability. We finish what we start and we build Uber to last. And when we make mistakes, we’ll own up to them.

We persevere.We believe in the power of grit. We don’t seek the easy path. We look for the toughest challenges and we push. Our collective resilience is our secret weapon.

We value ideas over hierarchy. We believe that the best ideas can come from anywhere, both inside and outside our company. Our job is to seek out those ideas, to shape and improve them through candid debate, and to take them from concept to action.
e make big bold bets. Sometimes we fail, but failure makes us smarter. We get back up, we make the next bet, and we go!

The new ethos at Uber’s headquarters may or may not be conveyed to its drivers. Maybe it should be.
Given the rising volume of hiring taking place at Amazon it is hard to ignore the company’s influence on hiring practices, the economy and even the environment. That doesn’t mean all is rosy at Amazon. Amazon continues to face obstacles of its own making including resistance to economic transformation in New York – where its headquarters bid was ultimately rejected – and claims of employment discrimination and retaliation. Uber has faced and continues to face similar challenges.

Still, Amazon is rapidly supplanting IBM, Xerox, AT&T, or even the U.S. Postal Service as an attractive and sought after place of employment. As has always characterized such employment, a job at Amazon could define one’s career path for a lifetime and ensure lifelong financial security with all of the related benefits.

In stark contrast to the prospect of a job at Amazon, Uber offers a very different employment prospect. I am not writing, of course, of the 22,000 headquarters and support personnel working at Uber. I am addressing the more than three million Uber drivers laboring on the expanding Uber platform – which now includes food delivery – around the world.
Uber offers the ultimate ad hoc employment opportunity with nary an interview at all without any of the security or benefits of a traditional “desk” job. Uber drivers may be fully or partially employed, depending on the amount of hours they work.

While the comparison of Amazon’s interview process with Uber’s ad hoc employment proposition is unfair it highlights two disparate paths to building value. Uber is supporting a bloated valuation freighted with billions of dollars in insurmountable losses. Amazon has created a solid foundation from a massive and expanding infrastructure supporting a global digital and physical delivery platform.

mazon has built a fortress of customer convenience and satisfaction surrounded by a moat of logistical expertise. Uber has constructed a sandcastle of loss-producing taxi rides on the backs of itinerant and under-compensated drivers. The recent driver strike on the eve of the IPO is but a hint of trouble to come.

The future of employment in the U.S. and around the world is at stake in Uber’s IPO today. We will all serve the machines in the future but will we be nothing but lumps of meat guiding vehicles and living hand to mouth? Or will we be masters of the machines and our own destinies – respected and nurtured.

The question goes beyond the prospect of employment. Both Amazon and Uber are of sufficient size to have measurable impacts on the economy and the environment.

Amazon not only takes responsibility for its impact on the environment, in many instances it has sought concessions from government authorities to ensure the provision of green energy sources. Uber, on the other hand, recklessly and ruthlessly violates local regulations and taxes transportation infrastructure while undermining public transportation resources.

Amazon provides living wages and benefits. Uber actively undermines the livelihoods of taxi drivers around the world – with the exception of those markets where the company has sub-contracted with local taxi services.

Both companies pose a burden to transportation infrastructure. Amazon delivery vehicles and delivery agents routinely impede traffic in major cities. Uber has been blamed for worsening traffic conditions in most cities where the company operates. The implications for emissions are obvious.

As Uber executives and investors ponder the long-term viability of the company today it may be time to reconsider the treatment and compensation of Uber drivers. This applies to Lyft, Yandex, DiDi, Heetch and all the rest. Are these companies building fortresses or sandcastles? Are Uber passengers as devoted to Uber as Amazon Prime customers are to Amazon?

Both Uber and Amazon offer convenience and cost savings, but the value proposition for customers, employees, the environment, and the economy are very different. One is sustainable and one is not.

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Chip Equip Trade War Collateral Damage

Chip Equip Trade War Collateral Damage
by Robert Maire on 05-13-2019 at 7:00 am
Categories: Semiconductor Advisors, Semiconductor Services
6 Comments

We have been very vocal and perhaps the first to warn of the risks to the semiconductor and semiconductor equipment industry from the China trade war with the US. It seems that the war is now fully upon us with the imposition of 25% tariffs by the US and promised retribution by China. The semiconductor industry is at the leading edge of the “made in China 2025” program that the White House would like to blunt, and along with it the current trade imbalance.

We had also warned that the stocks have gotten too far ahead of them selves since the beginning of the year as stocks have soared will fundamentals have wallowed and more importantly, ignored the increasing trade risk which has now returned home to roost.

There should be no question as to the fact that damage will be done to the chip industry, the only question is how much and how long lasting. Some of the damage may be long lasting enough to be permanent. Other damage may go away if we ever manage to find a resolution.

From a simplistic point of view we can look at things that are made in China and subject to the tariffs but we also have to dig deeper and think about potential responses from China and other second and third order impact that is possible.

Who makes stuff in China? AEIS & UCT among others
A number of years ago, Advanced Energy shut down all its manufacturing of semiconductor power systems in Colorado and proudly moved it all to Shenzhen China for lower cost. Virtually all of their semiconductor related product which is the majority of profitability is made in China and likely caught up in the trade war. Given that AE is already suffering from a cyclical down turn in the industry and customers are already putting increased pressure on costs, the cost of a tariff would eat much if not all gross margin. It would be very difficult, if not impossible to move manufacturing as it took years to move it to China in the first place.

UCT is another sub supplier to the industry with significant manufacturing in China. The type of components manufactured by UCT carry relatively low, teenage, gross margins that would be completely swamped by tariffs such that they would be in a loss condition. Again, moving would be difficult and time consuming. Their customers, like Applied Materials and Lam have become accustomed to the low prices and would not allow increases to be passed on in any significant way.

ICHOR could benefit
On the other hand, Ichor, which is a similar supplier to AMAT and Lam of products similar to UCT does not manufacture in China and thus not susceptible to tariff troubles. We think that Ichor could see significant share gains depending on tariff impact and length of the trade war. From an investor perspective we would think about a pair trade of long Ichor and short UCTT, on trade issues.

Rare Earth elements
The technology industry uses a lot of “rare earth elements” that are primarily supplied by China which China has limited access to in the past and could once again use them as a critical lever in trade wars.

The rare earth elements are much tougher problems to try to get around as there really aren’t other sources on the planet for many of them.

As an example, “cerium”, a rare earth element is used in slurries for CMP polishing. Cabot Microelectronics, CCMP, is the leading manufacturer of CMP slurries in the US.

Yttrium is a rare earth element used in etch chambers to protect the etch chambers from “eating themselves up” as part of the etch process. Etch tools are obviously made by Lam, Applied, Tokyo Electron among others.

There are 17 “rare earth elements” that are critical to technology and many have seen prior embargoes from China as well as huge price increases. These could all be used as very strong levers in trade.

Rare Earth Elements in Technology

More Interested in Soy beans and Coal
Unfortunately, the current administration seems more interested in soy bean exports and coal production as that is where its political base of support is strongest. The technology industry has not been a priority as it has not been seen as friendly or loyal to the current administration. Even Tesla could not get the new “brains” (CPU board) for its enhanced Model 3 self driving technology exempted from the China tariff list as the board is assembled in China, even though sourced in the US.
We would expect any tech company, not just chips, with product sourced in China will get hit. Conversely we would expect more protection of the more strategically important soy bean industry.

Export Tariffs
We are remain surprised that the administration hasn’t figured out the idea of export tariffs or restrictions, on technology that China needs for made in China 2025. China has long ago figured out the restricting the export of technologically important rare earth elements or jacking up prices was very effective. We on the other hand haven’t seemed to have figured out that China is desperate for our semiconductor equipment to power the many, many fabs it is building for made in China 2025.

I have said on a number of previous occasions that we are selling China the rope that they will use to hang us in technology, at the very least we could make it very expensive or hard to get.

Obviously this would have a huge negative impact on the semi equipment industry but it may be better in the long run.

We have already permanently lost market share to Japan

We don’t think that export restrictions or tariffs would hurt us any further than we have already been hurt. It is very, very clear that after the whole Jinhua fiasco, that Chinese fab builders are looking for any way possible not to buy US made tools.

Its not like there is any love lost between the Chinese and Japanese, but right now the Japanese look a lot more attractive than Americans.

Obvious beneficiaries are Tokyo Electron, Hitachi, DNS and a host of Japanese chip companies. Most impacted will be Applied and Lam in their dep and etch businesses, least impacted will be KLA as they have much less competition.

A further leg down in the cycle and slower recovery?

We had already been concerned about the length of the current down cycle. We think its clear that memory won’t recover before the end of the year and into 2020.

A significant , ongoing trade ware with China could prove to be a further leg down in the cycle, leading to a lower bottom, and an even further impaired recovery with a longer horizon.

Right now its too early to tell but we are concerned that neither side appears to be backing down in the least and both are continuing to escalate

The stocks
We think there is a lot more trade risk in the stocks than the downside we have already seen. Initial indications are not great for a negotiated peace and the tech industry, and chips in particular have a very high exposure.

We would look to avoid those stocks with high China trade exposure or subject to tariff or retaliatory moves from China such as those we have mentioned above.

We think there is a lot more trade risk in the stocks than the downside we have already seen. Initial indications are not great for a negotiated peace and the tech industry, and chips in particular have a very high exposure.

We would look to avoid those stocks with high China trade exposure or subject to tariff or retaliatory moves from China such as those we have mentioned above.

The group could remain under pressure as this will be a slow motion train wreck over a long period of time.

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The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!

The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!
by Daniel Nenni on 05-12-2019 at 4:00 pm
Categories: Events, IP, RISC-V, SiFive

Hello Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam
Our 2019 global symposiums and workshops have been hugely successful in promoting the RISC-V ISA and fostering expansive collaboration within the open-source community. It’s invigorating to see how the worldwide semiconductor ecosystem is energized and mobilized by the open ISA. One of the areas receiving the most attention is embedded intelligence. The RISC-V ISA is enabling designers and innovators to actively pursue solutions that employ enhanced embedded intelligence at the edge. The real-world applications of this are awesome and we are inspired by what we see!

The next leg of our tour is taking us to six cities in Europe. We’re so excited to meet the brilliant minds in and around Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam!

Cambridge Highlights
Imagination Technologies is our co-host in Cambridge. The symposium will take place on Monday, May 13, and includes a great lineup of speakers, tutorials and demonstrations. There will be keynotes by Naveed Sherwani, CEO of SiFive, and Andrew Grant, senior director of vision and AI at Imagination Technologies. There will also be presentations by Krste Asanovic, chairman of the board at the RISC-V Foundation, a member of the faculty from the computer laboratory at the University of Cambridge, IAR Systems, SecureRF and lowRISC. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Cambridge event, please visit: https://sifivetechsymposium.com/agenda-cambridge/

Grenoble Highlights
This symposium will take place on Wednesday, May 15. There will be presentations by Krste Asanovic, chairman of the board at the RISC-V Foundation, a graduate student from the LCIS laboratory at Grenoble INP, and presentations by SecureRF and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Grenoble event, please visit: https://sifivetechsymposium.com/agenda-grenoble/

Stockholm Highlights
With Qamcom as our co-host, this event will take place on Friday, May 17, and will include a powerful lineup of speakers. There will be keynotes by Krste Asanovic, co-founder and chief architect at SiFive, and Olof Kindgren, senior digital design engineer at Qamcom. There will also be presentations by a professor at KTH, The Royal Institute of Technology, IAR Systems, Antmicro and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Stockholm event, please visit: https://sifivetechsymposium.com/agenda-stockholm/

Moscow Highlights
SiFive and Syntacore are jointly hosting the symposium in Moscow on Monday, May 20. It will feature several presentations by key industry veterans and luminaries. There will be keynote presentations by Alexander Redkin, CEO of Syntacore, and Krste Asanovic, co-founder and chief architect at SiFive. There will also be presentations by IAR Systems, UltraSoC and other ecosystem partners. A lead researcher from ISP RAS (Russian Academy of Sciences) will also be presenting. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Moscow event, please visit: https://sifivetechsymposium.com/agenda-moscow/

Munich Highlights
Mentor is our co-host in Munich. This event will take place on Thursday, May 23, and features a great lineup of speakers. There will be a presentation by Krste Asanovic, chairman of the board for the RISC-V Foundation, and keynote presentations by Sunil Shenoy, senior vice president and general manager of the RISC-V Business Unit at SiFive, and Petri Solanti, senior field applications engineer at Mentor. There will also be presentations by IAR Systems, Rambus and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Munich event, please visit: https://sifivetechsymposium.com/agenda-munich/

Amsterdam Highlights
This symposium will take place on Wednesday, May 29. Some of the highlights include a keynote presentation by Sunil Shenoy, senior vice president and general manager of the RISC-V Business Unit at SiFive. There will also be presentations by Imagination Technologies and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Amsterdam event, please visit: https://sifivetechsymposium.com/agenda-amsterdam/