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Jump-Starting Full-Stack AI

Jump-Starting Full-Stack AI
by Bernard Murphy on 07-03-2019 at 5:00 am
Categories: AI
2 Comments

In the semiconductor world when we hear “full-stack” we think of a chip, chipset or board with a bunch of software, which can be connected to sensors of various types on one end, trained networks in the middle and actuators on the other side. But of course that’s not really a full-stack. The real thing would be deployment of an entire AI system such as an autonomous robot that can pick items from warehouse shelves, or a wearable medical device enabling disease management pathways, or an industry 4.0 process control and monitoring systems. Somebody else builds those, right, but how? This is still a very new domain in which everyone is feeling their way. If you’re not Amazon and you don’t know how to start, or even what expertise you need to spin up in-house to get a prototype working, you’d probably like some help.

The AI Lab Team

That’s where ICURO comes in. They build what they call AI system accelerators, intelligent technology solutions for businesses. I think of it as intelligent system design and prototyping as a service. This is obviously a bit different than regular XaaS services; here you get a full-stack AI system unifying the power of machine learning, machine vision, sensor fusion, embedded processors, robotics, and security to demonstrate immediate value in your business application.

Pulling this off obviously takes more than silicon, software and AI expertise. I talked to Bipin Thomas, President of ICURO at their AI systems lab in Santa Clara. That lab is itself an indicator that this is a different kind of company. While they’re building and prototyping AI products and solutions for their clients, ICURO’s core value is in the range of expertise they have acquired in architecting, developing and integrating those products.

They build on state-of-the-art hardware and software wherever available. So for example they use platforms like NVIDIA Xavier and AMD APU for ML inferencing. They use top of the line 4K cameras, inertial measurement systems, LiDARs, ultrasonic sensors, etc. For ML they connect to standard platforms for neural network definition and training – TensorFlow, Caffe and Darknet. And for navigation they use Visual SLAM and/or LiDAR SLAM together with ORB SLAM for localization. In a different example, a hospital provider used ICURO for pilot studies of health monitoring based on the Apple watch. So you can see that they provide a pretty broad range of AI solutions and services connecting underlying technology capabilities to end-user use-cases.

These are just some examples. As a full-stack AI solution provider, they want to provide help not only to end-users but also to component providers who want to project their value through demonstrator platforms. I know of at least one chip customer who is working with them for exactly this reason. I know of another who is looking for help in building use-case expertise for their general-purpose robot. This domain is so big and complex that very few companies are beyond looking for help; ICURO is already working with several Fortune 500 companies.

To cover all these bases, Bipin has built a team with a wide range of expertise:

  • Machine learning – to define and drive neural network training and optimization for inferencing
  • Sensor fusion – we casually throw this term around but making it work in a real application is still an art
  • Embedded systems – for all aspects of the embedded software stack
  • Edge architectures – for sensing and actuation along with reasonable power, communications and security
  • Mechatronics – for the mechanical aspects of actuation

Bipin is very proud of this full-stack AI systems lab in the heart of Silicon Valley. He has deliberately chosen not to recruit seasoned veterans, even in these domains. Instead he staffs the lab with recent graduates, not locked into fixed ways of solving problems in this still-evolving domain. The lab in his view is his secret sauce, a unique way to architect and build out full-stack AI systems. And he walks this walk. When prospects or partners visit, they don’t get slideware, they get hands-on demos. Which of us wouldn’t take a working demo over death by PowerPoint? You can learn more about ICURO HERE.

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#56DAC Update – What’s New at Concept Engineering

#56DAC Update – What’s New at Concept Engineering
by Daniel Payne on 07-02-2019 at 10:00 am
Categories: Concept Engineering, EDA

Concept Engineering, DAC56

I first connected with Gerhard Angst of Concept Engineering over 15 years ago, because I was using their SpiceVision PRO tool to visual SPICE netlists received from customer designs to be debugged in a FastSPICE circuit simulator. The ability to visualize a transistor-level netlist was simply essential to quickly understanding what the topology of a totally new netlist was, without having to hand-draw it, which was never a fun or accurate process. At #56DAC I met up with the team to ask them, “What’s New this year?”

NASA-JPL

I love all things space related, so was interested to hear about NASA’s Jet Propulsion Laboratory and how their missions to Mars and Europa, a Jupiter moon are using a couple of tools from Concept Engineering:

  • E-engine (automatic schematic generation engine for aerospace and automotive tools)
  • EEvision (visualization platform for aerospace and automotive)

Engineers at JPL follow a model-based approach that uses requirements to drive all aspects of a new design. Using E-engine and EEvision the development team members will have system and harness visualization abilities, and because the data is in the cloud they can see what they need quickly and it’s always up to date. Engineers won’t have to manually draw schematic diagrams in order to communicate with each other, because the new visualization tools will automatically generate just the portions they need to collaborate with.

The specific JPL projects using these new tools include:

  • Mars Sample Return – robots collect and return samples to Earth
  • Psyche Mission – journey to a metal asteroid between Mars and Jupiter
  • Europa Clipper – does Jupiter’s moon Europa have conditions suited for life

New VISION Features

Customers are constantly asking for new features in order to save time in their engineering tasks, so with version 6.11 of the Vision products they are getting several new abilities.

  • Speed and capacity for the largest SoC designs
  • Split-screen mode for easier debug and cross-probing
  • Selected objects have more extensive reporting
  • Easier visualization of parasitic extracted netlists
  • Better drag-and-drop between apps
  • Improved parsing of Verilog and VHDL designs
  • Parsing of SPICE netlists with macro models
  • Exporting Verilog netlists better supports simulation flows
  • SPICE netlists have automatic logic recognition
StarVision, auto-generated schematic

There are four types of Vision products, it all depends on the level of engineering abstraction that you’re working on:

Summary

The team at Concept Engineering has been busy over the past year and continue to expand the product features of their VISION tools, and the aerospace engineers at NASA-JPL are more effective in their tasks by using more automation instead of manual methods. Visualizing your designs can be quickly done at various levels of abstraction: transistor, gate, RTL. Documentation for service personnel is made easier by always being up to date, instead of behind several versions, because the auto-generated schematics are created directly from the CAD design data.

Schematic created directly from CAD design data

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An Important Next Step for Portable Stimulus Adoption

An Important Next Step for Portable Stimulus Adoption
by Daniel Nenni on 07-02-2019 at 5:00 am
Categories: AMIQ EDA, EDA

Portable stimulus has been a hot topic for a couple of years in the EDA and semiconductor industries. Many observers see this approach as the next major advance in verification beyond the Universal Verification Methodology (UVM), and the next step higher in abstraction for specifying verification intent. The basic idea is to create high-level models that can be used by EDA tools to generate test cases automatically. Yes, that sounds rather like the sort of constrained-random simulation tests supported by SystemVerilog, and even longer by the e language, both well-established standards. Let me explain what’s new.

Note first that Portable stimulus is also standardized; Accellera released version 1.0 of the Portable Stimulus Standard (PSS) at the Design Automation Conference (DAC) last year and version 1.0a in February to clean up a few things. But PSS is different from SystemVerilog and e in at least three important ways. I already mentioned the higher level of abstraction, and this enables the portability at the heart of the other two differences. PSS tools can generate test cases that scale from block/IP level through subsystems to complete SoCs/systems, and also from simulation through emulation, prototyping, and actual chips.

A recent post by Jim Hogan provides lots more information on the history and goals of portable stimulus and the standard. It’s easy to see why there’s so much interest in his topic. The idea of writing one abstract, portable model that can generate test cases for every phase of an SoC project is really attractive. I’ve talked with PSS tool vendors Breker, Cadence, and Mentor, and they all assured me that adoption is going well. There’s a fourth vendor in the PSS camp, AMIQ EDA, and my colleague Bernard Murphy discussed their initial support for portable stimulus in a post about six months ago.

Since then, I’ve had several interesting conversations with AMIQ EDA’s CEO, Cristian Amitroaie, about different aspects of their Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and their Verissimo SystemVerilog Testbench Linter. Cristian mentioned that the initial support they provided for PSS in DVT Eclipse IDE has been expanded, so I talked with him about a key new feature: scenario generation and visualization. Their tool now has the ability to analyze the stimulus being specified in a PSS model and display possible scenarios that satisfy the abstract specification.

Why is this so interesting? For one thing, a large number of valid scenarios can be generated from a single PSS model. It’s not easy for the engineer writing the model to visualize the details of the scenarios that could be generated.  Sometimes there are multiple ways to “solve” a PSS model to generate valid scenarios, and some of them may not be at all obvious (or even intended). The ability to visualize detailed scenarios can be very helpful in terms of determining whether or not the abstract PSS model is correct.

Due to the degree of parallelism available in a modern SoC, there may be dozens of processors and other engines running code, numerous I/O ports sending and receiving data, multiple memories with multiple channels and multiple levels of caches, and a bevy of buses tying all this together. Effective SoC verification requires exercising all this activity simultaneously. PSS models and the testcases based on the generated scenarios have the power to do this, but again it can be hard to picture how this all works without solving for valid scenarios and displaying them. I asked Cristian what happens if their tool cannot generate a valid scenario. He said that DVT Eclipse IDE provides detailed information about the generation process to help users fix the PSS model.

It seems to me that this new solving and visualization feature is a natural extension to the other capabilities that DVT Eclipse IDE offers for PSS code. The tool can parse code and find a wide variety of syntax and semantic errors, including those detectable only when multiple models have been compiled together. It also provides quick-fix proposals, hyperlinks to jump to declarations and usages, context-sensitive auto-completion of PSS constructs, structural views for browsing type and component hierarchies, project database queries, rename refactoring, and source code formatting.

I’ve been convinced for some time that a powerful IDE can make learning a new language much easier and save time in common operations even for the experts. This is certainly true for AMIQ EDA’s PSS support in DVT Eclipse IDE. The language is still novel for many engineers, while features such as scenario generation and visualization benefit both new and advanced users. I’d like to thank Cristian for sharing his thoughts with all of us, and I wish you luck as you adopt PSS.

To learn more, visit https://dvteclipse.com/products/dvt-eclipse-ide

Also Read

With Great Power Comes Great Visuality

Renaming and Refactoring in HDL Code

I Thought that Lint Was a Solved Problem

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An AI Accelerator Ecosystem For High-Level Synthesis

An AI Accelerator Ecosystem For High-Level Synthesis
by Bernard Murphy on 07-01-2019 at 10:00 am
Categories: AI, EDA, FPGA, Siemens EDA
1 Comment

AI accelerators as engines for object or speech recognition (among many possibilities), are becoming increasingly popular for inference in mobile and power-constrained applications. Today much of this inferencing runs largely in software on CPUs or GPUs thanks to the sheer size of the smartphone market, but that will shift as IoT volumes quickly overtake these familiar devices. IoT applications are generally very cost and power-sensitive, yet also demand higher performance from the inference engine to recognize more objects or phrases in real-time, so that they can deliver a competitive user experience.

Cost, power and performance are generally critical to differentiation for these devices and standard hardware platforms can’t rise to competitive expectations; this is driving the popularity of custom AI accelerators. However there is no standard architecture for these engines. Certainly there’s a general approach – convolutional neural nets (CNNs) or similar networks, but details in implementation can vary widely, in numbers and types of layers, window sizes, word sizes within layers and even in temporal versus spatial architectures.

So how does a system architect go about building differentiation into her CNN engine when she’s not really a hardware expert? One obvious choice is to start the design in an FPGA, at least for prototyping. This defers ASIC complexities to a later stage, but RTL-based design for the FPGA can still be a huge challenge. A much more system-friendly starting point is C++.

Suppose for example you want to build a spatial accelerator – a grid of processing elements (PEs) which can parallel process sliding windows on an image (this approach is getting a lot of press, see for example Wave Computing). You’ll first want to define your base PE design then interconnect these in a grid structure. The PE element needs to read in image data and weights, then compute partial sums. In addition, depending on how you choose to implement communication through the grid, you may forward weight and image data info through the PE or perhaps around the PE. Next you’ll array and interconnect these elements to build up your grid.

All of this can be expressed in a C++ description of the grid, with instances of classes for the various components. There are some limitations in coding to ensure this can be mapped to hardware, for example word widths are going to have to map to real hardware, and you’ll want to experiment with these widths to optimize your design. This is where the Catapult ecosystem helps out.

You don’t want to start with basic C++ datatypes and functions because these can’t always be optimally mapped; for example, basic C++ doesn’t offer word support with arbitrary widths and general-purpose packages that do won’t natively connect to hardware. The AI ecosystem instead provides predefined HLS (high-level synthesis) datatypes as C++ classes with overloaded operator functions to map your C++ description to a hardware equivalent, while also allowing you to tune in parameterizations consistent with that mapping.

It also provides a math library, including not only the usual math functions for those datatypes but also matrix and linear algebra functions common in neural net computation. Such functions can come in different implementation options:, such as fast with some small error or a little slower with higher accuracy. As you’re running your C++ trials you can easily experiment with tradeoffs like this. Functions provided cover all the usual list for neural nets, including PWL functions for absolute value, log, square root, trig, activation functions for tanh, sigmoid and leaky ReLU, and linear algebra functions like matrix multiply and Cholesky decomposition A lot of these functions also have MatLab reference models which you will probably find useful during your architectural analysis.

You also get a parameterized DSP library for functions like filters and Fourier transforms and an image processing library, configurable for common pixel formats and providing functions you are likely to need, like color conversion, image scaling and windowing classes for 2D convolution.

So pretty much you’ve got everything you need to take you from an input image (or speech segment) through widowing, to all the CNN functions you’re going to need to complete your implementation through to identification. All in C++, using which you can do initial tuning in MatLab. You can experiment with and verify functionality and performance at this level (waaaay faster than simulation at RTL) and, when you’re happy, you can synthesize directly into an RTL implementation where you can characterize power and area.

Since your accelerator will sit in a larger system (an FPGA or an SoC), you need to connect with that system through standard interfaces like AXI. Catapult HLS takes care of you here through interface synthesis. Ultimately, at least for your prototype, you can then map your design to that FPGA implementation so you can check performance and accuracy at real-time speeds.

To round this out, the ecosystem provides a number of predefined toolkits/reference designs: for pixel-pipe video processing, for 2D convolution based on the spatial accelerator grid structure I mentioned earlier, and for tinyYOLO object classification. No need to build these from scratch; you can start with the toolkits and tweak to get to the architecture you want.

This is a pretty complete design solution to help bridge the gap between AI system design expert needs and the hardware implementation team. You should check it out HERE.

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Two Fun Things To Do at SEMICON West on July 9, 2019

Two Fun Things To Do at SEMICON West on July 9, 2019
by Randy Smith on 07-01-2019 at 10:00 am
Categories: EDA, ESD Alliance, Events, IP

 

I will be at SEMICON / EE Design West on Tuesday, July 9, 2019, and so should you!

Quantum computing will be a hot topic at SEMICON West and on Tuesday, July 9, the IBM Quantum Computer will be on display at the Smart Design Pavilion in the South Hall (Moscone Center) from 10:00am to 5:00pm. It looks like no other computer I have ever seen and should make for a fun diversion at SEMICON West.

What is quantum computing? It is a new approach to logic, or a new approach to computing, depending on how you look at it. Many of the tougher problems we would like to solve today just cannot be run on even the biggest classical computers. The world needs a new kind of computer. Quantum computers utilize the quantum mechanical phenomena of superposition and entanglement to create states that scale exponentially with number of qubits, or quantum bits. That is more than a bit to wrap your mind around. But we all should starting learning about it now.

Of course, IBM has been developing a Full Stack Quantum Software package since a computer isn’t not useful if you cannot program it. You can even try it out now. There’s a lot to see and hear about quantum computing at SEMICON WEST, including a TechTALK and a keynote. You can get more info on the IBM Q computer activities at SEMICON WEST here, and more details on IBM’s quantum computing efforts here.

Every summer for more than a dozen years, the Heart of Technology (HOT) has thrown a party to raise money for a worthy charity, typically one aiding children or young adults. This year will be no different as the HOT event of the summer will take place on Tuesday, July 9 at the John Colins Lounge located at 138 Minna Street in San Francisco, coinciding with SEMICON West / ES Design West being held at nearby Moscone Center. The event will run from 5:30pm to 10:00pm. Click the link above to register in advance.

Heart of Technology is a charity accelerator helping local charities hold special events, sometimes far larger than any events they would typically undertake. Jim Hogan is the leader and founder of HOT. I have helped Jim with these events for a long time. We now have a large number of volunteers to help us put on these events, and of course, we are very grateful to the companies that sponsor these events.

We seek donations from many local companies in the electronics industry, including EDA and semiconductor IP. The official tally is over $180k since 2012, but I am sure it is much more, we just never really kept track as the funds went straight to the charities. I remember we raised over $30k (from an auction and gate receipts), plus donated food, at an event supporting Second Harvest in San Jose around 2004. Some recent events have given more than $50k to local charities and scholarship funds. I imagine the correct number is likely close to half a million dollars by now.

This year’s event will have a slightly different focus. “We are always running into inequality with gender in sciences and engineering. The aim is to get more girls and women interested in the sciences. The SEMI organization has a foundation that has such a program, so that’s what we’re raising money for this year.” Several corporate donations have already come in, but we can use everyone’s help. We are expecting a strong turnout this year as the event becomes accessible to an audience far larger than DAC.

This year’s venue is also a bit smaller than usual as we deal with the transition year in EDA trade shows. If you are planning to go, badge holders at ES Design West and SEMICON West will be admitted with a suggested minimum $20 donation. Other guests can attend for a donation of $50. The venue is small, so please arrive as early as you can. The Methodics Ensemble, as well as the Dead Sea Fish, will be playing. Members of Jim Hogan’s band, Vista Roads, will be in attendance and may sit in with the bands that are playing. And I know from our past events, a good time will be had by all.

Now, go register for SEMICON West.

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Layoffs à la Fairchild

Layoffs à la Fairchild
by John East on 07-01-2019 at 5:00 am
Categories: John East
5 Comments

The “20 Questions with John East” series continues

You wouldn’t think that layoffs would be a subject that I’d want to talk about in my stories of  “Silicon Valley the Way I saw it.”  The subject is just plain distasteful!!  — Still  — layoffs were a major part of the valley’s culture back in the day.  To give a true picture of how it felt to work at Fairchild in the early 70s, this story must be told.

When Les Hogan and his heroes joined Fairchild, Fairchild had been losing money. As I look back on it, I imagine they might have been in the middle of a cash crisis.  Also, in looking back it seems that there wouldn’t have been a quick fix.  TI clearly had a superior cost structure to ours.  Our wafer sort yields weren’t good at all and we didn’t have an inexpensive plastic package to match the one that TI had developed. The picture from the top couldn’t have been rosy. One day Les Hogan was interviewed by someone in the financial press.  He was asked what he intended to do to stem the losses. His answer,  “That’s not a problem. We’re going to reduce the headcount by a third. That will get our spending back in line.”

That quote made the front page of the business section of the local newspaper.  It probably felt good to the investors when they read it, but it felt really, really bad to the people who worked there.  That was not what we wanted to hear!  And that was the beginning of some serious layoffs.

Once they started, it seemed like every Friday somewhere in Fairchild there were layoffs. TGIF didn’t apply at Fairch!! Everyone would go straight to the cafeteria Friday mornings. No one bothered going to their desk. Everybody was scared to death. Everybody needed their job and knew that there was a very good chance that they would lose it in the next few minutes. Lots of gallows humor. Lots of camaraderie. Everybody loved everybody else. There are no atheists in foxholes.  And then, they started.

There was a very well known “journalist” who covered the semiconductor industry in those days.  His name was Don Hoefler. I never met Hoefler.  I think he had worked at Fairchild at one time and that there was bad blood when he left. Maybe he had been fired?  Maybe an “Off with their heads” casualty? He started writing a weekly industry newsletter. It was always very negative towards Fairchild. Needless to say, the upper echelon at Fairchild were not enamored of Hoefler. I heard several times that anyone caught in possession of one of Hoefler’s newsletters was subject to being fired   – but that might have been just a rumor.  After all, we all read it (being careful not to get caught) but so far as I know, no one was ever fired for that offense.

One of Hoefler’s newsletters dealt with “Layoffs Fairchild style” describing how Fairchild employed three unique tactics for implementing lay-offs. The paging system layoff, the locked door layoff, and the retroactive layoff.  How did those work?

The Paging System Lay-off
This was the standard.  I witnessed this one many, many times.  —— It’s Friday morning. We’re all huddled together in the cafeteria.  Around 9AM the paging system cranks up. “Bob Martin 2867”.   —–   Everybody knew what that meant. Bob Martin (who was a real person and a really delightful guy) knew what it meant too. Bob or some similar victim would stand up and start shaking hands. After he said goodbye to everyone, he’d walk over to the phone and call 2867. 2867 was, of course, the HR department (Called “personnel” in those days). “Bob, this is Bill, can you drop by to see me?” That would be the last that anyone would ever see or hear of Bob Martin.

The Locked Door Layoff
I never saw this one, but Hoefler swore it happened.  I think it may have been used up at the R&D facility  — that’s where the best kept technical secrets resided. There was great fear in those days that company secrets would be stolen by people leaving the company. The Basic Data Handbook was the result of a lot of work that Fairchild rightly didn’t want to fall into the hands of the start-ups who were trying to eat Fairchild’s lunch.  On the other hand, anyone who was leaving for any reason would be tempted to take a copy of it on his way out.   How could you keep that from happening?

According to Hoefler, if you were going to lay off someone in possession of a lot of key knowledge, then the way to do it was to have the facilities department change the lock on the victim’s door the night before. Then, when the victim arrived in the morning and found his key wouldn’t open the door, he’d go see his boss who would then lay him off. That way he had no pre-warning and couldn’t sneak the key information out before the axe fell.

The Retroactive Layoff
This happened if you were unlucky enough to be selected for downsizing when you were out on vacation.  When the victim returned he was informed that he had been laid off and that there was good news and bad news:

“The good news is we gave you two weeks of severance pay.”

“The bad news is you were laid off three weeks ago.”

Perversely enough, I don’t think it was as bad for the victims as it might seem at first blush.  The valley was rife with start-ups and many of them were hiring.  I’d venture to guess that the victims got jobs that were as good or better in short order and that their careers played out better than they might have if they’d stayed at Fairchild.

This story may seem a bit frivolous  —  not to any particular point.  But there is a point.  It’s a snapshot of how Fairchild was back in the day, and to a lesser extent how the entire semiconductor community was.   It was seen by all and consequently shaped the thinking of future generations.  Jerry Sanders,  for example,  watched this unfold and used  it to mold some of the management theories that he would later employ.  (See my week #11 AMD story when it’s published in four weeks).  Jerry,  by the way, once said:

“Being fired by Fairchild was the best thing that ever happened to me.”

Next week.  RTL, DTL, TTL.  What was it?  Who cares?

See the entire John East series HERE.

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2019 GSA Silicon Summit and SiFive

2019 GSA Silicon Summit and SiFive
by Daniel Nenni on 06-28-2019 at 8:00 am
Categories: Events, IP, RISC-V, SiFive
2 Comments

Naveed Sherwani, President and CEO of SiFive, did the keynote for this year’s Silicon Summit. This is one of the premier events for the C level executives in Silicon Valley, absolutely. Naveed is one of the top visionaries for the semiconductor industry and he certainly did not disappoint this time or any other time in my experience.

Naveed started off comparing the semiconductor industry to the software industry. For example, their growth is 10x in 1 year while ours is 10x growth in 10 years. This is very relevant now that AI is driving the semiconductor industry because AI is software centric, right? The SemiWiki bloggers and I have been doing serious amounts of coverage on Artificial Intelligence. AI now drives the largest share of traffic on SemiWiki.com as it touches ALL of the market segments that we closely watch: IoT, Automotive, 5G, and Security.

Naveed did a nice AI overview and I now have the slides so here is a brief summary:

Fast Tracking Silicon and Systems Design for the Edge

The interesting thing here is that AI chips are domain specific so there will be no single provider like Intel used to be for CPUs and Nvidia for GPUs. The result being that systems companies will ultimately rule this domain ( as they now do with SoCs) with custom silicon when the AI market matures, my opinion.

This all started on the edge devices with mobile companies putting AI cores inside SoCs. These Neural Engines were used for facial recognition and other machine learning and inferencing tasks. Cloud companies are also making domain specific AI chips. Google announced Tensor in 2016 at the Google IO Conference. In 2018 Google announced the third generation TPU plus an edge TPU for cloud inferences. Other cloud companies have followed suit making custom silicon for their data centers.

The worldwide public cloud business is expected to grow more than 17% in 2019 to a record $200B+. In 2022 it should exceed $300B so spending a couple of hundred million on making your own chips to differentiate your cloud services is an easy thing to justify, right?

The result is a major semiconductor disruption, not unlike the fabless transformation we experienced in the late 1980s and early 1990s. Systems companies design chips differently than traditional fabless companies. They are not bound by chip margins since they do not sell the chips so budgets are much more flexible. Semiconductor ecosystem companies such as foundries, EDA and commercial IP companies have done quite well as a result. FPGA prototyping companies specifically have done very well since the systems companies have a significant software burden that can be addressed more quickly through prototyping and emulation. AI models are also fast moving so you definitely want to prototype.

Speaking to that, one of the slides Naveed used repeated the notion that 7nm chip development is too costly at more than $500M. This number has been floating around the ecosystem for some time and I have found it to be patently FALSE. Even if you include embedded software development it is not even close to $500M. eSilicon has already taped out some very large chips at 7nm for a fraction of that price. I have discussed 7nm design costs with some of the top fabless semiconductor companies in California and every single one of them laughed or smirked at the $500M 7nm chip price. And now I’m reading that 5nm chips will cost $600M?

SEMICON West is coming up so I will continue my inquiry into this FUD but you have to ask yourself “self, who is it exactly that benefits from this kind of 7nm smear campaign?” The answer of course is the analysts who are trying to sell their reports. Unfortunately, they are cutting off our noses to spite our faces since investment in fabless companies is at risk with such inflated propaganda, but I digress…

Naveed also mentions China which is appropriate since you cannot have a semiconductor discussion these days without talking about China. Naveed points out that China is leading the world AI funding with 48% compared to the US at 38% and this will continue in my opinion. Even so, I would say that in total, US funding will result in many more production chips than China since China is still relatively new at the fabless business while the US has 30+ years of experience.

According to Naveed the big difference between software and semiconductor design is development costs (true), development cycle (true), and too many experts needed (very true).

Naveed then transitioned into the SiFive value proposition for emerging AI chips. Remember, SiFive acquired ASIC provider Open-Silicon last year. The result is a cloud based do-it-yourself ASIC service featuring RISC-V 32 and 64 bit CPU cores and supporting IP in what Naveed calls “templates”.

SILICON AT THE SPEED OF SOFTWARE

Design RISC‑V CPUs in an hour. Get custom SoCs in weeks, not months. Impossible? Not anymore. Discover a fundamentally new approach to creating custom SoCs.

START DESIGNING

Bottom line: SiFive is all about removing the barriers to getting emerging fabless chip companies and new-to-chip-design systems companies into silicon. Design starts and finishes are the lifeblood of the semiconductor industry so I say BRAVO!

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Double-digit semiconductor decline in 2019

Double-digit semiconductor decline in 2019
by Bill Jewell on 06-27-2019 at 4:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

The global semiconductor market is headed for a double-digit decline for the year 2019 after a decline of 15.6% in first quarter 2019 from fourth quarter 2018. According to WSTS (World Semiconductor Trade Statistics) data, this was the largest quarter-to-quarter decline since a 16.3% decline in first quarter 2009, ten years ago. Most recent semiconductor market forecasts reflect this trend. 2019 forecasts range from -7.2% from IDC to -15.0%, our latest Semiconductor Intelligence forecasts. Other forecasts are in the range of -11% to -13%.

Available forecasts for 2020 show a return to growth, ranging from +5.4% from WSTS to +8.7% from Mike Cowan. Our Semiconductor Intelligence forecast for 2020 is +8.0%.

The reported first quarter 2019 revenues of the major semiconductor companies confirm the severity of the decline from fourth quarter 2018. The three largest memory companies all reported declines of over 20%. Samsung revenues were down 23% and SK Hynix revenues were down 32%. Micron’s quarter ended February 28 showed a 26% revenue decline from the prior quarter while its quarter ended May 31 showed an 18% decline. Micron sees early signs of a recovery in the memory market in the second half of calendar 2019. Its revenue guidance for the current quarter ending August 31 ranges from a 2% decline to a 10% decline, with a midpoint of a 6% decline. Samsung also sees demand stabilization from some memory applications.

Most non-memory semiconductor companies also saw major revenue falloff in first quarter 2019, ranging from STMicroelectonics’ -22% to Texas Instruments’ -3.3%. Qualcomm, Nvidia and Infineon showed low single digit revenue increases. The outlook for second quarter revenues of non-memory companies is mainly positive. MediaTek expects 17% growth from first quarter based on growth in smartphones in the seasonally strong second quarter. Nvidia guided to a 15% increase due to growth in gaming and artificial intelligence (AI) applications. Texas Instruments, STMicroelectronics and Infineon expect low single-digit quarter-to-quarter growth in second quarter, but the low end of guidance for each is a decline. Of the non-memory companies, only Intel expects a decline (-2.9%) based on channel inventory adjustments and concern over the U.S.-China trade issues.

The current weakness in the semiconductor market is due to a supply/demand imbalance in the memory market, weak key end equipment markets and global economic concerns. IDC forecast a 1.9% decline in smartphone unit shipments in 2019, following a 3.4% decline in 2018. IDC expects smartphones to recover to 2.8% growth in 2020. Gartner projected total PC plus tablet units will decline 0.7% in 2019, a slight improvement from a 2.5% decline in 2018. Gartner does not see a shipment recovery in 2020, with a decline of 0.8%.

Annual Change 2018 2019 2020 Source
Smartphones -3.4% -1.9% 2.8% IDC, May 2019
PCs & tablets -2.5% -0.7% -0.8% Gartner, April 2019
Global GDP 3.6% 3.3% 3.6% IMF, April 2019

The International Monetary Fund (IMF) sees global GDP growth decelerating from 3.6% in 2018 to 3.3% in 2019, bouncing back to 3.6% in 2020. The IMF cited the U.S.-China trade dispute, slowing consumer demand in Europe, and Brexit uncertainty in the UK as factors leading to the GDP deceleration in 2019.

The good news is the semiconductor market appears headed for recovery by the second half of 2019. The current slowdown is primarily due to memory and some inventory issues. End equipment markets are weak but should improve in 2020. GDP growth is slowing in 2019, but most economic forecasters do believe a recession is likely and growth should return to 2018 levels in 2020. Although a significant semiconductor market decline is inevitable in 2019, we at Semiconductor Intelligence feel confident with our 8% growth forecast for 2020.

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SPIE Advanced Lithography Conference – Imec design papers

SPIE Advanced Lithography Conference – Imec design papers
by Scotten Jones on 06-27-2019 at 10:00 am
Categories: Events, Lithography, Semiconductor Services, TechInsights

At the SPIE Advanced Lithography Conference Imec presented several design papers and I have had the opportunity to review the papers and speak with the authors. In this summary I am going to address three emerging areas in order of when I think they may be implemented from soonest to latest.

Specifically, I will discuss:

  1. Buried Power Rail (BPR)
  2. Backside Power Distribution
  3. Complementary FET (CFET)

Buried Power Rail

Logic designs are made up of standard cells. The size of a standard cell depends on metal pitch, cell track height, poly pitch and whether it is single or double diffusion break. For many years scaling was driven by metal pitch (MP) and poly pitch (PP) scaling, but MP scaling faces lithographic and resistance challenges and PP scaling has slowed due to device issues. The use of Design Technology Co-Optimization has led to track height scaling becoming a major scaling knob, but track height scaling also presents challenges.

Figure 1 shows scaling with a 40% per node area shrink goal.

Figure 1. Area scaling.

Scaling limitations also result in more restrictive design rules.

Figure 2 illustrates the evolution of designs by node.

Figure 2. Design evolution with node.

 From figure 2 it can be seen that as we have moved to smaller nodes 2D poly and metal layouts have given way to 1D layouts and more complex Middle Of Line (MOL) interconnect schemes.

Figure 3 presents the number of fins versus track height. The height of a cell is the MP multiplied by the number of tracks. As the MP and number of tracks are reduced there is less room for fins and fin depopulation is required.

Figure 3. Scaling challenges.

 As cell heights have scaled from 9, to 7.5, to 6.5 and eventually 5 tracks the number of fins per cell has been reduced from 4 to 3 to 2 and eventually 1 fin. This will also result in decreased drive current unless something is done to otherwise optimize the device.

Power rails for cells (Vdd and Vss) are typically some multiple of MP (see upper left in figure 3). At 5 tracks the spacing is so tight that in order to realize the cell the power rails must be moved out of the MOL interconnect layers and down into the substrate as Buried Power Rails (BPR). An illustration of BPR is presented in the CFET section.

BPR present fabrication and material challenges with the BPR having to survive subsequent high temperature transistor fabrication steps. The material used for the BPR has to be selected for low resistance and high thermal stability. One target material is Ruthenium but Ruthenium is very expensive.

 Backside Power Delivery

While BPR helps with the layout challenges to get to a 5-track cell, there are still issues with IR-drop due to the rising resistance of the very thin interconnect lines. Backside power delivery addresses these issues by creating large power distribution lines on the underside of the device and connecting them up to BPR using Micro Through Silicon Vias (µTSV).

Figure 4 illustrates the backside power delivery process flow.

 Figure 4. Backside Power Delivery process flow.

 The backside power delivery process flow begins with a wafer that has buried power rails.

  1. The wafer is temporarily bonded to a carrier wafer.
  2. Wafer thinning is performed.
  3. The backside passivation is patterned.
  4. High aspect ratio through silicon vias (TSV) are formed and filled.
  5. Backside power rails are formed.

The process requires extreme wafer thinning and precise location fo very small TSVs.

 Complementary FET (CFET)

The CFET concept is simple, instead of fabricating nFET and pFET devices next to each other they are stacked, see figure 5.

Figure 5. CFET scaling concept.

 As was discussed in the section on buried power rails as track height is scaled down fin depopulation occurs with a single fin expected for a 5 track cell.

The CFET design break the p to n separation distance bottle neck and can enable a 4 track cell height with 2 fins, see figure 6.

Figure 6. CFET scaling.

 Vertically stacking nFET and pFET devices creates and interconnect challenge and requires more complex middle of line (MOL) approaches. Figure 7 illustrates a 4 track cell in cross section and figure 8 illustrates a 3 track cell in cross section.

Figure 7. Cross section of 4 track CFET cell.

Figure 8. Cross section of 3 track CFET cell.

Finally, figure 9 summarizes the advantages of the CFET concept.

Figure 9. Benefits of a CFET.

 Conclusion

The challenges of continued logic scaling are being met with innovative new process designs. Buried power rails and backside power distribution address power distribution requirements for low resistance in small areas.

CFETs present an opportunity to address horizontal scaling limits with a 3D logic approach.

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Integrated SIMs Will Unlock IoT Growth

Integrated SIMs Will Unlock IoT Growth
by Bernard Murphy on 06-27-2019 at 5:00 am
Categories: 5G, IoT, IP, Security, Synopsys
2 Comments

I’m a believer that connectivity for the IoT at scale (the trillions of devices that the industry predicts) has to be cellular. This is partly based on reach, particularly outside urban areas, but is mostly based on the financial implications of that scale. Yes, you can build infrastructure for say local Wi-Fi support with backhaul to cellular or wired internet, but that comes with capital and on-going operational costs, together with varying levels of quality and security which each organization has to bear. In an age of virtualized everything, this makes no sense. We let the people who specialize in building and running hyperscale datacenters offer us cloud computing. We should let the people who specialize in offering global, interoperable mobile communications (MNOs) provide our IoT communications infrastructure.

Example ISIM implementation

This comes with the added benefit that MNOs are motivated to ensure that anyone who connects is authorized to do so, through the authentication services provided by the SIM cards we know so well. SIM cards would be wildly impractical for the IoT – too easy to hack and too painful to maintain across massive networks of edge devices. This has driven development of embedded SIMs (eSIMs), over-the-air (OTA) programmable SIM devices now available in consumer products such as the iPhone XR and XS.

But eSIMs are still separate chips, adding bill of materials cost and power consumption to your product, neither desirable in IoT devices which are generally expected to be very cost-sensitive and depending on very infrequent maintenance to change batteries. The natural next step should be to integrate the eSIM functionality into your SoC, right?

That turned out to be not so easy. I talked to Michael Moorfield, head of Product at Truphone and Ruud Derwig, Sr staff engineer at Synopsys about this. Truphone is an interesting company providing (among other things) an MVNO service (mobile virtual network operator) particularly for international businesses and IoT solution providers needing seamless mobile connectivity around the world. So they know a thing or two about cellular, MNO services and particularly eSIMs. They already provide a full software stack ecosystem for eSIM for the IoT. Now they’ve been working with Synopsys to move this to the next step – integrated SIM (iSIM).

So what’s the big deal in translating an eSIM into an IP? According to Ruud, that’s where this gets tricky. SIMs are held to a very high security standard, much higher than the sadly still common “we should really do something about security in this product” IoT expectation. MNOs don’t want anyone stealing access, from them or from a legitimate customer, since that access is billable; stealing access here connects very directly to stealing money. So SIM security design is very similar to the security you find in chipped credit cards. It needs to be shown to be as near unhackable as we know how to build today (there is no industry standard yet for this, but it wouldn’t be surprising to see one emerge). This means unhackable not just against logical/software attacks, but also against semi-invasive attacks (timing, DPA and RF side-channels) as well as more invasive attacks through power or clock glitching.

The hardware subsystem has been crafted by Synopsys and Truphone around existing DesignWare components: the ARC SEM processor, crypto accelerators, a secure external memory controller, a true random number generator and other features, all providing multiple mechanisms for protection and tamper detection. Notable in the software stack sitting on top of this hardware is the Java Card platform, the same system used in credit card chips.

Add to this that Truphone is already GSMA-accredited for generating and processing sensitive SIM and MNO data and I have to believe whatever iSIM standards will be, they’ll look pretty much like this solution. You can learn more about this joint development HERE.