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Electronics design mega-trends have been a transformational force for the world. As shown in blue in Figure 1, the first wave of electronics consisted of centralized computing and the leaders in the field included companies such as IBM, Digital Equipment Corporation (DEC), Wang, and others. Fundamentally, these technologies provided productivity solutions for the administrative (G&A) functions for the global business enterprise. With this shift, the finance, human resources, and administrative functions of global business were disruptively impacted. Gone were the days of a sea of admins doing paperwork.
Figure 1: Mega-Trends (Anew-da.ai)
Electronic Design Automation was born inside the large companies such as DEC as well as flagship university institutions such as UC Berkeley before spinning out into an independent industry. Initially, EDA for system design (PCB) and semiconductor design were of similar size. However, as Moore’s law drove increasing functionality onto a semiconductor chip, EDA tools for semiconductor design scaled accordingly. Over the last 50 years, semiconductor design has grown to dominate the business of EDA.
The next wave consisted of edge computing devices (red in Figure 1) such as personal computers, cell phones, and tablets. With this capability, companies such as Apple, Amazon, Facebook, Google, and others could add enormous productivity to the advertising and distribution functions for global business. Suddenly, one could directly reach any customer anywhere in the world. This mega-trend has fundamentally disrupted markets such as education (online), retail (ecommerce), entertainment (streaming), commercial real estate (virtualization), health (telemedicine), and more. In terms of design, the big shift was the focus on mobile battery based devices in highly integrated cost-sensitive products. To support this new system paradigm, the EDA design chain had to be updated to understand and support a wide variety of methods which minimized power dissipation. In addition, supporting integrated mechanical, packaging, system design became a necessity.
What is the next mega-trend and what does it imply for the required evolution of EDA capability ?
Today, we are at the beginning of the next major disruptive cycle caused by electronics. This cycle consists of embedded sensory devices (sometimes known as Internet of Things), local intelligence systems (sometimes known as machine learning), and global intelligence (sometimes known as cloud resources). Broadly called AI/IoT, these three technologies will disruptively impact nearly every market segment where in-field sensing with computing can solve interesting problems. Medical devices, mining, agriculture (land or ocean), space operations, and of course autonomous vehicles, are rich examples of this paradigm.
Table 1: Short LifeCycle (SLC) vs Long LifeCycle (LLC) (Anew-da.ai)
AI/IOT moves electronics onto the “edge” and also into the world of Long LifeCycle (LLC) products. Table 1 contrasts the system level characteristics between short and long cycle products. Similar to the shifts in previous mega-trends, the AI/IOT paradigm requires EDA to support several new capabilities. These include:
Design for Supply Chain Resilience: Today, the semiconductor supply chain is dominated by SLC products, and this is not expected to change. LLC products face a circumstance where they need to design in such a manner as to absorb the enormous churn created by the SLC products on the semiconductor supply chain.
Design for Reliability: Today, most of the semiconductor supply chain is optimized for the consumer life cycles. To gain the required reliability characteristics for long cycle products one must build the reliability through system design techniques.
Design for Functional Evolution: Many LLC products are embedded in the field with high replacement costs (ex.. smart buildings). The probability for requirements evolution over time is very high, so designing for functional evolution is another key requirement of this product segment.
Design for System Maintainability: Field maintainability is a key issue for LLC products. Thus, key ideas such as automatic calibration of sensors or automated detection of fault becomes very important in this design space.
Many of these issues have existed for many years in markets such as satellites and indeed agencies such as NASA have invested in internal solutions. However, similar to spinout from large information technology OEMs from the 1980s, there is a need for commercial EDA solutions to support the LLC design paradigms.
For those interested in further reading on these topics:
There are significant advances in communication protocols happening all around us. The Peripheral Component Interconnect Express (PCIe) Gen 5 standard is delivering the needed device-to-device performance to support artificial intelligence and machine learning applications as well as cloud-based workloads. The rapidly evolving Compute Express Link (CXL) standard is delivering CPU-to-device and CPU-to-memory communication to enable next-generation data center performance. Both are critical enablers for next generation systems and require support in the form of semiconductor IP to be deployed. PLDA has made recent announcements regarding significant milestones for both PCIe and CXL, which is not a common occurrence. I wanted to look a bit closer at both of these announcements to see how PLDA is at the leading edge with advances in both PCIe 5.0 and CXL.
What was announced here was a demonstration showcasing a stable PCIe 5.0 link training (32 GT/s) featuring excellent signal integrity with a Broadcom® PCIe 5.0 PHY. PLDA used its XpressRICH® IP Controller for PCIe 5.0 with Broadcom’s PCIe 5.0 PHY IP. Several different scenarios were presented to highlight the exceptional signal integrity of the combined IPs. PLDA explained that the demo serves as a quality guarantee for SoC designers using the combined solution of PLDA’s PCIe 5.0 controller and Broadcom’s PHY IP.
The demonstration included:
Exceptional signal integrity via an eye scope provided by a SerDes pattern generator and PCIe 5.0 Tx compliance patterns monitored on a scope
Stable PCIe link training at 32 GT/s proven by a crosslink connection of two boards monitored using Xilinx Vivado ILA and a Viavi PCIe analyzer
Backward PCIe compatibility at 16 GT/s, 8 GT/s, 5 GT/s, 2,5 GT/s that were demonstrated in a real environment
Stephane Hauradou, CTO at PLDA commented, “It’s a great milestone for PLDA technical teams to achieve stable PCIe Link Training at 32 GT/s. The complexity and the challenges involved in reaching this result have evolved with the different PCIe generations and we wanted to further demonstrate our PCIe 5.0 solutions, even though they are already proven in silicon.”
The CXL announcement was also about performance and interoperability. This time, between PLDA’s XpressLINK™ CXL IP, running on a PLDA FPGA-based add-in card and Intel’s development platform equipped with pre-production “Sapphire Rapids” processors. The PLDA XpressLINK controller implements the CXL.io, CXL.cache, and CXL.mem sub-protocols as specified in the recently released CXL 2.0 specification and is already being designed-in at leading technology companies.
The demonstration was conducted at Intel’s Industry Enabling Labs as part of a long-term collaboration between PLDA and Intel’s industry enabling group. Stephane Hauradou commented, “Today’s demonstration of interoperability between PLDA’s XpressLINK CXL IP, which delivers the lowest latency in the industry, and a cutting-edge CPU like pre-production Intel Sapphire Rapids processor, is a critical step in assuring SoC designers of the robustness of our CXL implementation”.
Dr. Debendra Das Sharma, Intel Fellow and Director of I/O Technology and Standards Group, Data Center Group also commented, “CXL will be a foundational interconnect technology in the data centers and networks of the future. The availability of third party silicon IP like the PLDA XpressLINK CXL Controller IP lowers integration risks and helps ensure quicker proliferation of the CXL protocol across the industry ecosystem.”
PLDA XpressLINK and XpressLINK-SOC CXL IP are highly parameterized CXL controller soft IP designed to the latest CXL specification and architected for SoC, ASIC, and FPGA implementation. XpressLINK and XpressLINK-SOC are available for licensing immediately and are already designed at several leading-edge technology companies.
Summary
PLDA is a technical leader in high-speed Interconnect IP. These two recent announcements separated by only a few weeks demonstrate their commitment to supporting the latest standards with a focus on interoperability and robustness. To probe further:
Over the last 40 years, Bernard has worked with semiconductor and EDA companies in hands-on, management and consulting roles in engineering, sales and marketing. He most recently co-founded Atrenta where he created and led the development of SpyGlass, retiring as CTO when Atrenta was acquired by Synopsys. Post-retirement, he’s been an active blogger for SemiWiki. He’s also written a couple of books under the SemiWiki label and he independently advises a number of clients on marketing content
Why did you decide to write The Tell-Tale Entrepreneur?
Over the last 40 years, I’ve created, suffered and edited more than my fair share of biz and tech communication. Which has reinforced my view, widely shared, that our communication is pretty bad. Pitches, blogs, white papers aiming to convince are at best unconvincing, at worst painful. What’s curious is that, from engineers to CEOs, think we’re good at PowerPoint. Yet we’re terrified at the thought of writing. PowerPoint feels like a familiar template, communicate-by-numbers. Word has no template; we have to start from a blank sheet, hence the terror. Which suggests the format is beside the point, we suck at communication either way. PowerPoint just lulls us thinking we don’t.
I started out just as bad, but I worked hard to improve. Through a lot of trial and error I believe I figured out the problem. I want to pass this on, not through a boring how-to book but through an entertaining set of short stories. Designed to show you how to make your communication just as engaging.
How is storytelling different and why is it better than other ways to communicate?
Take PowerPoint as a reference. It’s well established and has great value in structured contexts where efficient information transfer is the goal. Status updates, project planning, training, technical due diligence. But it’s weak in persuasion. Where you need to convince a client, prospect, investor that you have the best product for their needs. Or you are their best possible partner. Or you failed to deliver what you promised and now must rescue the relationship.
These are times when slides are the wrong answer. You have to connect emotionally with your audience – building excitement around a new direction, dealing with fear of possible failure, maybe pointing out pitfalls that you already understand well. Or convincing them there will be no more mistakes. Eyeball to eyeball conversations.
The best way to guide that conversation is through a story. You’re looking at them (not slides), they’re looking at you, and you’re telling them a story, appealing to their emotions.
Storytelling isn’t a new idea. What makes your approach different?
Storytelling is a very old idea. Today we relegate stories to entertainment, expecting that business communication needs a more professional approach. Our brains don’t agree. We’ve been telling stories from beginning of time. Not just to entertain but also to pass on wisdom, culture, beliefs, laws. Our brains are wired to receive stories efficiently, motivating us to action. Not so for data and logic dumps. That’s why we find PowerPoints so boring and start scrolling through texts, emails, anything rather than listen to the speaker.
Instead tell a story. Stories are naturally engaging, especially when they sound roughly relevant to the audience’s goals. We want to know what’s going to happen next. Calling the hero to adventure. Facing tests together, proving ourselves a worthy mentor. The big challenge where it could all go wrong, but somehow our hero makes it through, now stronger, more capable. And the final challenge. Much more interesting than texts and emails. They learn what you can do for them along the way, in a context they recognize.
Storytelling is big in marketing now. Tons of advice online on how to do it – blogs, whitepapers, companies who want to advise you (for a fee). But there’s something a bit odd about this advice. It all seems to come in the same business communication standard format: explanations, bullet lists and charts. You want to learn how to tell stories. Wouldn’t it be better to do that by reading stories?
That’s my innovation – I explain how to tell stories by telling you stories.
Who do you think will find value in this book?
Anyone in tech who must communicate with customers, prospects, investors. Who wants to reach markets through blogs and white papers. Those who aspire to sell their company. All will relate to experiences in these stories. And will I hope will be inspired to re-imagine and improve their own stories, based on these examples.
The book is also written for a general audience. Anyone interested in real stories drawn from different phases in the lives of tech ventures. Technology plays a role in these stories but isn’t primary, so I’ve simplified quite a lot. People, opportunities, challenges, growth are the most important elements.
These stories are for everyone, but especially for us communicators in tech. Most important, I hope you will begin to understand why our audiences are thirsting for stories, not more death-by-PowerPoint.
Where can we find the book?
The Tell-Tale Entrepreneur is available for pre-order on Amazon and will be released on January 26th, 2021.
The next transition from current FinFET devices at advanced process nodes is the “nanosheet” device, as depicted in the figure below. [1]
The FinFET provides improved gate-to-channel electrostatic control compared to a planar device, where the gate traverses three sides of the fin. The “gate-all-around” characteristics of the nanosheet device provide further improvements in electrostatic control, surrounding the device channel. This is typically reflected in a more optimal subthreshold slope, or SS. The SS relates to the change in device gate input voltage that results in a factor of 10X change in leakage current. A smaller SS implies both faster device switching and, significantly, a reduction in the static source/drain leakage current and leakage power dissipation. (More on SS shortly.)
Additionally, the nanosheet device offers more design flexibility. Whereas the topology of the FinFET device width is quantized (Weff ~ ((2*fin_height) + (fin_thickness))), the width of the nanosheet device is defined by EUV lithography (Weff ~ nanosheet_perimeter).
The effective nanosheet width can be further extended by stacking multiple channels vertically, with the gate material fully surrounding each of the individual nanosheets. The design flexibility and improved device characteristics make this technology option very attractive.
There are major challenges to the introduction of nanosheet processing to production, however. Here are but a few:
isolation of individual “ribbons” of the nanosheet device channel
The nanosheet device is fabricated in an epitaxial layer. The horizontal device sheet is embedded within other epitaxial-grown layers – e.g., a silicon layer sandwiched by epitaxial layers of different composition, such as SiGe/Si/SiGe/Si/SiGe. (As will be described shortly, the close similarity in crystalline structure between Si and Ge is critically important.)
The formation of the nanosheet device “ribbon” requires a very selective etching process. The epitaxial layers above and below are to be removed, while not etching the remaining device channel. For multiple, stacked nanosheets, this etching process also needs to be anisotropic, so that all the sacrificial epitaxial layer material between nanosheets is fully removed.
the high-K gate oxide dielectric surrounding the exposed nanosheet ribbons needs to be extremely uniform, with excellent adherence
The oxide defect density and interface trap density (for injected “hot” carriers) needs to be extremely low. (An annealing step in a hydrogen gas environment is commonly included as part of the device process flow.)
similarly, the metal gate material stack needs to be deposited uniformly throughout the structure, fully enclosing the stacked sheets
The gate stack is typically comprised of an initial metal-to-oxide “workfunction” layer (e.g., TiN), followed by a metal to fill the gate volume, such as Tungsten. (Atomic layer deposition (ALD) is truly an amazing technology.)
a low resistance source/drain device node needs to be fabricated adjacent to the channel, to reduce Rs and Rd
An epitaxial growth step (with a high dopant concentration) is used to increase the S/D volume next to the channel, suitably isolated from the gate by a sidewall separation oxide. (Other FET topologies also use a similar raised S/D epitaxial step.) Additionally, the S/D doping profile needs to ensure a low contact resistance to the first-level metal.
“device engineering” needs to introduce significant strain into the channel material, to improve the free carrier mobility, and thus, the drive current
For several process generations, from planar to FinFET device topologies, various techniques have been employed to introduce strain into the channel material crystal – tensile strain for higher nMOS electron mobility, compressive strain for higher pMOS hole mobility. “Stressor” material dielectric layers were added on top of planar devices. The raised S/D epitaxial regions also transfer strain to the channel.
Of particular concern is the disparity between the electron and hole mobility in silicon. Process development engineers continually strive to improve the hole mobility, to bring it closer to the electron mobility. A key advance in this area has been the addition of Ge to the S/D epitaxial growth step, and ultimately, to the pFET channel – i.e., a Si(x)Ge(1-x) crystalline structure, providing a compressive strain and vastly improved hole mobility. (Seasoned circuit design veterans will remember the days when pFET device widths were 2.5X-3X the nFET device width, to compensate for the hole versus electron mobility disparity. With strain introduced during SiGe pFET fabrication, that difference is vastly reduced.)
The transition to a nanosheet channel of very small thickness exacerbates the difficulty in providing improved pFET device characteristics. At the recent IEDM conference, Intel presented a detailed paper on how their nanosheet engineering has addressed this challenge. [2] The rest of this article summarizes the highlights of their presentation.
pFET Nanosheet Fabrication
An overview of the nFET and pFET nanosheets are depicted in the figure below.
(The focus of the IEDM Intel presentation was on pFET engineering.)
As mentioned above, compressive strain in the channel is key to a high-performance device. This is achieved by the following:
the epitaxial nanosheet for the pFET channel is Si(0.4)Ge(0.6)
the raised S/D epitaxial growth volume is also SiGe
the substrate directly below the nanosheet consists of Si and a “strain relief buffer” (SRB) layer of Si(0.7)Ge(0.3)
This buffer layer offers an intermediate crystalline transition from the bulk silicon substrate, and provides some degree of additional channel strain.
Parenthetically, the crystal lattice constants of Si and Ge differ by only 4.2% — Si = 0.543nm, Ge = 0.566nm. As a result, the Ge/Si ratios are fully miscible.
The figure above also illustrates other process engineering constraints:
a highly doped top layer on the S/D regions is required for low contact resistance
the gate oxide needs a low defect and trap density (with a very aggressive high-K material thickness – e.g., an interface dielectric to the channel and a subsequent HfO2 layer)
The transition from the nanosheet thickness (~5nm) to large p+ S/D nodes requires detailed process engineering, to electrically isolate the gate from the S/D, and introduce compressive strain into the pMOS channel from the doped SiGe epitaxy. (More on this step shortly.)
The figure below summarizes the overall Intel pMOS nanosheet fabrication steps, and provides a TEM cross-section of a single nanosheet device – NS thickness = 5nm, Lgate = 25nm, width = 100nm, EOT oxide = 9.1Angstroms.
Nanosheet fabrication requires several unique steps, combining conformal materials deposition with both isotropic and anisotropic (directional) etch technology. Additionally, the isotropic etch technology needs to be very selective to different materials composition.
The figures below from Reference [3] illustrate an overall flow for the general case of multiple stacked nanosheets. (The Intel IEDM discussion focused on materials and compressive channel strain for a single pMOS nanosheet device.)
The starting material is alternating layers of undoped Si/SiGe epitaxy. A “dummy” top-level gate is patterned, followed by conformal deposition of an oxide and (highly) anisotropic etching of the oxide and Si/SiGe layers to form the starting nanosheet stack. The next steps are critical, as depicted below.
The sidewalls of the exposed gate areas are selectively etched, to provide a recessed volume for conformal oxide deposition. Anisotropic etching of this oxide results in a stack where the gate areas have lateral spacer oxide, while the sidewalls of the channels remain exposed, and serve as the seed for source/drain epitaxial growth.
Nanosheet nMOS devices in Si require processing with highly selective etching of the adjacent SiGe layer, exposing the Si sidewall for S/D epi growth. Nanosheet pMOS devices require high etch rates of Si, exposing the SiGe sidewall for S/D epi growth. Extensive process R&D (and materials chemistry) has been applied to optimize the Si/SiGe “etch rate ratios”.
After S/D epi growth, the dummy gate and epitaxial gate layer are etched away (again, very selectively to the now released nanosheet channel “ribbons”). After a pre-clean, the high-K gate oxide materials are deposited on the ribbons, followed by the (workfunction and low-resistance) metal gate stack, both steps using atomic-layer deposition (ALD). Contact “trenches” down to the bottom nanosheets are opened and filled with metal, completing the nanosheet fabrication. (There are chemical-mechanical polishing (CMP) steps in this flow, as well, for surface planarity prior to etching.)
Parenthetically, it should also be mentioned that extensive process R&D has been invested to select the specific crystalline orientation that optimizes the strain-enhanced carrier mobility, etch rate selectivity, and S/D epitaxial growth.
Nanosheets and the parasitic transistors
Returning to the Intel presentation for their optimized compressive strain pMOS nanosheet, IDS-VGS curves for different devices are shown below (Lgate = 55nm and 25nm).
As might be expected from the superior electrostatics of the gate-all-around configuration, the subthreshold slope measured for these devices is exceptional. (Intel did not describe their engineering approach toward establishing the threshold voltage of the pFET device.)
Of particular interest is the behavior at the S/D-to-substrate interface. The nanosheet structure results in a parasitic transistor between the metal gate surrounding the bottom nanosheet and the substrate. The S/D contact to the nanosheet also serves as the S/D connection for the bottom parasitic transistor. To evaluate the magnitude of this parasitic device current, Intel fabricated and measured a test vehicle consisting of only this parasitic transistor – the experimental results are shown below.
The leakage currents from this device are much less than for the nanosheet, indicating suitable suppression of this “sneak” current. (To further reduce this parasitic current, a punchthrough stop dopant region could be introduced below the S/D contact.)
VDD Optimization
For high-performance applications, designers are seeking to boost the supply voltage toward the technology maximum. The limitations are due to the increased Ioff leakage at higher voltages. A higher drain-to-source electric field in the channel result in drain-induced barrier lowering (DIBL) current, and very high drain-to-gate fields result in gate-induced-drain-leakage tunnel current (GIDL). The figure below indicates that VDD = 0.9V is feasible for this technology, before the GIDL current increases exponentially (strained-SiGe, Lgate = 25nm, t_NS = 5nm).
Summary
Nanosheet devices are the next evolution in advanced process nodes after FinFETs. Yet, nanosheet fabrication requires several unique process steps – e.g., ALD, epitaxial growth, and highly selective etch rate ratios. Of specific concern is the requirement to introduce compressive strain in the pMOS nanosheet channel, to improve the hole mobility. A unique combination of Si and Si(x)SiGe(1-x) material layers and epitaxy are required. Intel recently discussed their results on optimizing pMOS nanosheet engineering. I would encourage you to review their presentation.
-chipguy
References
[1] Jeong, J., et al, “Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub-5nm Node SoC Application”, IEEE Access, Volume 8, 2020.
[2] Agrawal, A., et al, “Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application”, IEDM 2020, paper 2.2.
[3] Cheng, K., et al., “Nanosheet with Changing SiGe Percentage for SiGe Lateral Recess”, US Patent No. 10,312,350B1, June 4, 2019.
The goal of this Podcast Series is to bring semiconductor experts together to get to the truth about the matter at hand. We’ll get right to the point and not exceed 30 minutes of your time. If you have a topic you would like us to cover please post it on SemiWiki.com and we will get right to it.
After introductions from Daniel Nenni and his podcast partner Mike Gianfagna, Dan and Mike discuss the high profile semiconductors enjoy today. This bright spotlight is a relatively recent phenomenon. How the semiconductor market began and what forces shaped the current climate are discussed. Many of these topics will be the subject of future episodes.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
Today is SemiWiki’s 10th anniversary so an extra special Happy New Year to all! It has been an exciting 10 year adventure for sure and I hope it can continue for another 10 years, absolutely.
2020 brought in a record amount of content, readers and members. Our readership grew 70% YoY in 2020 according to Google Analytics which is a big number. Readership grew 15% YoY in 2019 which was about average. Total SemiWiki.com readers over the ten years are now more than 4 million with more than 50M blog views!
In 2020 the new SemiWiki job board attracted 395,943 views and the community calendar recorded 404,224 views. The new press release section recorded 1,480,953 views and the company wikis received an additional 158,743 views. We published 670 blogs that recorded more than 6M views, another SemiWiki record. Thankfully, SemiWiki 2.0 is easily scalable in the cloud, another handy 2020 addition.
For this amazing success we thank you all. What’s coming up for SemiWiki in 2021 you ask?
First and foremost, our new podcast series “Semiconductor Insiders” starting tomorrow Jan 2, 2021. This will be a weekly series hosted by myself and the top 2020 SemiWiki blogger Mike Gianfagna.
“The goal of this Podcast Series is to bring semiconductor experts together to get to the truth about the matter at hand. We’ll get right to the point and not exceed 30 minutes of your time. If you have a topic you would like us to cover please post it on SemiWiki.com and we will get right to it.”
Mike and I did the introductory EP1 which is titled “Why are Semiconductors so Sexy”. EP2 is “Moore’s Law Dead or Alive” with Dr. Walden Rhines. EP3 is “Tomorrow’s Semiconductors” with Jim Hogan and EP4 is “Can China Really Become Self-Sufficient in Semiconductors” with Robert Maire. February is still in the planning phase so submit your topics in the comments section.
Secondly, virtual events are so much easier for us to cover and I expect that to continue in 2021. More events, more expert coverage, more content for all. We are finishing up IEDM 2020 coverage this month and ISSCC is up next then SPIE and DVCon.
Thirdly, we added the SemiWiki Webinar Series in 2020 which was attended by thousands of people. Webinars are still the best virtual event for ROI in all regards. This year we will do more of the same with maybe a slight twist or turn.
Fourthly, the SemiWiki LinkedIn group now has more than 21,000 members. LinkedIn is our top social media channel so please join as my guest and support our community. SemiWiki also has a LinkedIn company page where we post relevant press releases from the semiconductor ecosystem. Please follow us there as well. If you want your press release or news event posted send it to admin at SemiWiki dot com.
Fifthly, something you all may not know, SemiWiki has internal email so members can connect and discuss topics at hand in private. A record number of email was sent this year and I expect that to continue since we cannot connect and network at live events.
Finally, here are the top ten most viewed blogs is 2020:
If you have ideas or suggestions on how SemiWiki can improve in 2021 for the greater good let me know via SemiWiki email. It would be a pleasure to speak with you.
This area of automating the design of Flat Panel Displays (FPD) is so broad that it has taken me three blogs to cover all of the details, so in brief review the first two blogs were:
The following Q&A is with Chen Zhao, from Empyrean, and he’s an AE that’s been with the company since 2014.
Q: IC designers use DRC and LVS tools, so how’s the process different with curvilinear FPDs?
The function of the layout verification tool is to check whether the layout meets the design rules and electrical rules, and whether the layout is consistent with the schematic diagram, etc. 1
It is essential for eliminating errors, reducing design costs and reducing the risk of design failure. General layout verification techniques are developed for rectangular layouts. The emergence of curvilinear-shaped designs poses a great challenge to the layout verification technology. It is necessary to develop new algorithms suitable for curvilinear-shaped designs based on traditional computational geometry algorithms 2, 3.
The grid is used in the layout to determine the position of the graphics, and the vertices of the graphics are on the grid points. The rotation of the layout may cause the vertices and grid points of the graphics to be misaligned, causing the two sides that were originally perpendicular to be no longer perpendicular. Take the next figure as an example. After rotation, “a” and “c”, and “a” and “e” no longer maintain 90 degrees, DRC may report false errors, such as the minimum distance for “a-c” or “d-e” is not enough. At this time, it is necessary to add support angle tolerance rules, by filtering out errors with features such as “small edges” and “small corners” to avoid false errors. Of course, this method has certain risks. The user can output these errors to a specific file to distinguish these minor errors from important errors and check important errors first.
In addition, if you can merge the graphics before rotation, you can also avoid errors.
Layout rotation causes false DRC error
Due to the rotation of the layout, the error increases. LVS may cause the device extraction failure when extracting the circuit netlist.
An MOS transistor example, after rotation, the source and drain terminals do not intersect with the gate due to the dislocation of the vertices and grid points, and the transistor extraction fails. The above DRC methods to eliminate false errors, such as supporting tolerance, merging before graphics rotation, etc., are also applicable to LVS.
Layout rotation causes false LVS error
ArgusFPD parallel hierarchical layout verification tool developed by Empyrean focuses on the FPD market. It faces the verification needs of ultra-large-scale layouts and advanced design methods such as curvilinear-shaped designs. It provides customers with layout verification solutions that can meet the needs of FPD design sign-off requirements.
Q: How do you simulate large circuits such as an FPD array?
The traditional SPICE simulation of the FPD circuit and the SPICE simulation of the integrated circuit have nothing special except to support the TFT model used in the FPD circuit. As the resolution of the FPD increases, the scale of the FPD circuit becomes larger and larger, and it is unrealistic to use traditional SPICE circuit simulation to achieve a full-panel circuit simulation.
The computational consumption of circuit simulation is mainly divided into two parts, namely SPICE device model calculation and circuit matrix solving 4. For full-panel large circuit simulation, matrix calculation basically occupies more than 90% of the simulation time. Therefore, one way to speed up the circuit simulator is to speed up the matrix solution. Based on this, EMPYREAN’s circuit simulator EsimFPD ALPS developed an adaptive matrix solver 5. It contains a variety of matrix solvers. It can automatically select different matrix solvers, according to different matrix properties (such as dense matrix, sparse matrix, etc.), which can greatly improve the simulation while ensuring the SPICE accuracy of circuit simulation speed
Another method of circuit simulator acceleration is to optimize the simulation algorithm considering the structure of the FPD circuit.
Q: What is the topology of an FPD array?
The structure of the FPD is composed of light-emitting pixel units arranged in a two-dimensional array. As shown below, the cell is the pixel unit. There are three sub-pixels in the cell: red (R), green (G), and blue (B). From the circuit level, the FPD is the top-level circuit, and the cell is the sub-circuit of the next level, and the sub-pixel circuit is the sub-circuit of the next level.
Hierarchical structure of FPD circuit
Each cell has the same circuit structure, and each sub-pixel circuit in the cell also has the same circuit structure. These cells have the same circuit structure, and their states are also similar when working, so we can define the cell as a basic unit. The circuit parts with the same structure and the same state only need to store and simulate only one basic unit, and the simulation data is shared with other units, which greatly reduces the simulation time and the required memory.
In addition, using the heterogeneous computing structure of CPU+GPU is a new direction to improve the speed of full-scale circuit simulation 6, 7.
Q: What is your approach for RC extraction to get parasitics into a more accurate netlist for simulation?
EMPYREAN’s parasitic RC extraction tool RCExplorer FPD provides pixel and touch panel capacitance and resistance simulation analysis tools for a variety of FPD design application scenarios. Based on the parasitic capacitance resistance extraction technology of the accurate three-dimensional field solver, the adaptive meshing technology is adopted to accurately simulate the coupling capacitance.
The 3D field solver is based on electric field analysis and uses numerical calculation methods to solve the Laplace equation. The problem of solving capacitance can be transformed into solving the induced charge of a conductor under a certain bias voltage. This problem can be solved by solving the following electromagnetic field equations 8.
The RCExplorer FPD tool also supports pixel-level liquid crystal capacitance extraction, as shown next. At the same time, it can support Gate-on capacitor extraction.
Pixel liquid crystal capacitance extraction
Q: Can you extract a touch panel design layout?
Yes, the RCExplorer FPD can simulate the capacitance of the touch panel in the touch panel design. Due to the large size of the touch panel design and the high requirement for capacitance accuracy, it’s challenging to ensure both high accuracy and performance requirements. The tool uses a meshing method based on following advanced technologies, such as, a mixture of triangle elements and trapezoid elements; intelligent meshing engine automatically determines the degree of density; efficient and adaptive mesh encryption 9, 10; multithreading and multitasking parallel calculations, etc., to ensure the calculation accuracy and calculation speed to meet the design requirements. At the same time, the tool also supports Floating Signal and Finger settings.
With the parasitic capacitance and resistance extracted by RCExplorerFPD, users can perform post-layout analysis to check whether the design load is within an acceptable range, and help designers optimize the layout load design.
Touch Panel RC Extraction
Q: How are the thermal-electrical characteristics analyzed for FPD arrays?
High-precision OLED device current control is extremely important to the uniformity of OLED FPD light emission, and so it is critical to ensure the stability of power and ground potential 11. The EMPYREAN Artemis FPD high-resolution full-panel layout thermoelectric analysis tool analyzes the power/ground voltage drop distribution, current density distribution, and temperature distribution of the FPD, which can effectively help designers optimize the design.
This tool adopts advanced techniques such as accurate resistance calculation method, cascade array netlist output, hierarchical fast calculation method, heat conduction and heat convection, etc., which can quickly and accurately perform full-panel analysis.
The tool uses an array-based accurate resistance calculation acceleration method. The entire flow uses a two-dimensional field solver to calculate the highest precision resistance network, and uses the pixel array hierarchy to quickly calculate the voltage and current distribution of the overall resistance network. It calculates the power and ground potential of each TFT.
FPD voltage distribution analysis
With the wire resistance between the nodes of the resistive network and the voltage across the nodes, together with the device voltage and current information, we can calculate the power value at each node of the entire panel.
With the power distribution, according to the mixed model of heat conduction and heat convection, we can get the heat distribution of the panel.
FPD temperature distribution analysis
Q: Why is it important to have Mark Rule Checks (MRC)?
MRC inspection is an important part of the design flow after the mask layout is completed. EMPYREAN’s MRC tool provides the Mask and Glass design engineers with tools to check the correctness of Mark placement. Mark is an important reference for process alignment of exposure, etching and other machines, and has zero tolerance for errors. The MRC tool provides an automated Mark inspection method to improve the reliability of Mark design. It can check more than ten rules and their combinations, such as forbidden zone, symmetry, standard Mark position comparison, and provide clear and easy-to-understand annotation cartoons to mark the location of errors, such as forbidden zone inspection errors.
MRC forbidden zone inspection
Q: What are challenges of the largest panel masks?
The Split Panel function provides an FPD design engineer with the function of cutting the panel layout into multiple mask layouts. Split Panel is an essential function in large-size stitching design. When the size of the Panel exceeds the size of the exposure machine, one exposure cannot complete the production of a large-size panel, and it is necessary to stitch the design for multiple exposures to finally complete the production of a panel. Based on the layout of the large-size panel and the size of mask, the Split Panel cuts the panel through guideline or cartoon direct cutting method, thereby dividing it into multiple mask layouts.
Schematic diagram of Split Panel
The Split Panel function can automatically call the Mosaic function. If the boundary between two adjacent exposures is a straight cut, the human eye can clearly distinguish the exposure dividing line in the light-emitting area of the panel, because the human eye is more sensitive to the shape of the long strip.
In order to circumvent the above problems, it is necessary to perform fuzzy cutting at the exposure boundary. The method is to randomly select pixels for photolithography within the range parallel to the division line on both sides of the abstract exposure division line in the light-emitting area (AA) . For example, for a certain layer, if a certain pixel is to be exposed in shot A, its layer graphics will be kept in shot A cell. On the contrary, use a rectangle of the same size as the pixel outline to completely cover it. The goal is to make the dividing line non-linear and irregular, avoiding the problem that the human eye can recognize regular boundary. The function of randomly dividing pixels into two or more shot cells is called a Mosaic function.
Mosaic function in Split Panel
Q: What does the production department receive from the FPD design group?
After both the Mask and Glass layouts are completed, the Mark information needs to be extracted to the production department. At this time, the Job File function is required. The Job File function automatically extracts the coordinate list of the specified marks and outputs the process file according to the specified template or rules for the post-layout steps. Generally speaking, the output process file will be used as the reference coordinate file for machine work and other production processes.
Job File data
Summary
In the three blog series we’ve covered a lot of details on how modern FPD designs can be automated through the successive steps of: circuit schematic, layout, SPICE device modeling, SPICE circuit simulation, RC layout extraction, IR-drop analysis, thermal analysis, design verification and mask analysis.
Empyrean has been focusing on the FPD design automation area since 2012, so give them a call when your team ventures into this product development area. Expect new developments from Empyrean in the area of design kits for OLED and Micro LED devices, and improved optoelectronic hybrid simulation. Going beyond electrical simulation of FPD, there are many areas for expansion.
Empyrean FPD technology outlook
References
Carl Ebeling. “Gemini II: A Second Generation Layout Validation Tool”，Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD-88), pp. 322-325, November 1988
Zhou Peide, “Computational Geometry: Algorithm Design and Analysis”, Tsinghua University Press, 2005
Thomas H. Cormen, Charles E. Leiserson， “Introduction to Algorithms”, China Machine Press, 2006
Liu Weiping, Zhou Zhenya, Cai Yici, “A Hybrid Acceleration Algorithm for Post-layout Parallel Circuit Simulation”, Journal of Computer-Aided Design and Graphics Theory， 28（11），2016-2020， 2016
Yang Liu, “A new generation high performance parallel circuit simulation tool”, China Integrated Circuit, October 2016
Lifeng Wu, “Enable Full Panel Circuit Simulation to Improve Brightness Uniformity”, Invited Paper, 9th International Conference on CADTFT, ShenZhen, China, November, 2018
Lifeng Wu, “Exploring New Tides of EDA”, Invited Paper, 25th Asia and South Pacific Design Automation Conference (ASPDAC), Beijing, China, January 2020
Lu, T., Wang, Z., and Yu, W. “Hierarchical Block Boundary-Element Method (HBBEM): A Fast Field Solver for 3-D Capacitance Extraction.” Microwave Theory & Techniques IEEE Transactions on 52.1:10-19.
Lu Taotao, Wang Guanghui, Hou Jinsong, Wang Zeyi, “Hierarchical h-Adaptive Computation in VLSI 3-D Capacitance Extraction”, Chinese Journal of Semiconductors, 543-549，2002
Jinsong Hou，Zeyi Wang，Xianlong Hong，“The hierarchical h-adaptive 3-D boundary element computation of VLSI interconnect capacitance”，ASPDAC，1999
J. Sun, “IR-drop compensation for large size AMOLED”, IDW Tech. Dig., pp. 183-184, December 2011
Probably the least appreciated and most critical thing I spend my time on when driving custom silicon projects is setting up the entire framework to get everyone talking and in rhythm with each other. Only supplier selection is more critical to the project’s success than this.
All system custom silicon projects where the silicon is not designed and manufactured in-house by the system company require at least two companies to directly interface with each other: the system company and the silicon supplier company. Each one of these two companies has other companies they subcontract work to. These become critical to the custom silicon development process at some stage of the project.
System company teams
Typically, the system company works with a contract manufacturer (CM), and that CM interacts with the silicon supplier whenever there is an FA from the build. The CM sends units back for analysis at the silicon supplier’s lab. The CM also needs to discuss with the silicon supplier the types of reels to be used for shipments, part markings, and eventually the CM will be submitting POs for the MP ramp.
The system company has many cross functional teams. Any or all of these teams could be involved in the integration of this component into the system: software, firmware, security, EE, ME, system reliability, component engineering, PCB design, thermal team, signal integrity, silicon management, system project management, sub-system teams and their project management, battery team, antenna/RF team, test fixture team, GSM, and/or legal.
Silicon supplier company teams
In parallel, the silicon supplier interacts with a package and test contractor, and a foundry for wafer manufacturing. The silicon supplier could also be subcontracting external design houses, quality testing labs, failure analysis labs, etc… Some silicon suppliers have in-house foundries, and package and test in-house, but most do not. The system company generally will not interact with the foundry or the package and test subcontractor EXCEPT if they are interested in aggregating their volumes to get better pricing and terms. So for example, a system company may be buying many different chips from different silicon suppliers, but most are using the same foundry or the same packaging houses. They may decide to go directly and tell those foundries to aggregate their total volumes when quoting wafer or package prices to the silicon supplier for the parts for which they are the end customer. In this way, the system company obtains a price reduction.
The silicon supplier company has some core teams which at some point will be interacting with the system company. These are: design (analog and digital) team, validation/apps team, test team, layout team, verification (AMS, DV and analog) team, package, sales and marketing teams, FAEs, and software/firmware teams.
If there are not already enough teams, people and companies involved, add to the mix that typically the system company, the silicon supplier and their subcontracted parties are in different countries/regions.
Here are some basic things that need to be implemented to manage this complexity of human and technical challenges:
Communication.
You will need to implement multiple regular interactions to keep people aligned and informed. The main meetings that need to be programmed are: regular sync call between the system and silicon supplier teams, internal cross functional sync meeting at the system company, in person design reviews and in person vendor selection reviews, meetings to obtain phase sign off from executives for all phases, and many other contact points as needed to deep dive on items. Make sure to establish a ticket system to track actions throughout the entire process . You will need to document a lot, and share between different sides as needed. CustomSilicon.com offers some packages that manage some or all of these interactions.
Ensure to have a process to manage the system custom silicon engagement.
CustomSilicon.com implements a process, and manages both the system and silicon companies such that there is a really strong connection between all teams, the deliverables are clearly communicated, and the development phases are signed off by all stakeholders such that there is cross functional and multi company alignment at every stage of the project. The process should be captured in the contracts, and the sign offs should be used as triggers. This is not legal advice, and I am not lawyer, so please ensure to seek legal counsel to draft good contracts. The silicon manager will drive the sign offs with the system company, and also drive to closure all issues with the silicon supplier such that at the end of a phase a concise precise escalation can be presented to the system company executives for their approval.
Establish a clear stakeholders list, establish what authority each of them has, and for what aspect of the project.
One of the least appreciated, and most critical aspects of driving cross functional teams is that it is imperative that no one usurps someone else’s rightful authority over the domain for which they are responsible. One very pernicious human factor that destroys effective collaboration is the practice of calling “working meetings” or “executive update meetings” with decision makers to push a one sided agenda. The people that call the meeting leave out other stakeholders who hold some contrary views. A healthy debate over the proposals is prevented. Then an attempt is made to gain approval from the decision makers without presenting all facts and views. This type of political maneuver will seriously derail cross functional team collaboration. It will also destroy trust and goodwill in the program. The silicon manager MUST not let this happen by ensuring everyone that is a rightful stakeholder is signed off for each phase and included in discussions directly relevant to their domains. The other issue that needs to be addressed is not allowing people who are NOT rightful stakeholders to impede or block progress from occurring. Sometimes they demand to be included in meetings to which they have no agenda items to cover. They may also want to “vote” on decisions to which they are not rightful stakeholders. Sometimes it is ok to allow non-stakeholders to sit in meetings. But in my experience this can backfire as you then start seeing how these political maneuvers have some malicious intent which later becomes clear. The silicon manager then has to deal with the blowback to keep the program on track. So to keep the peace and sanity, it is very important that everyone that is a stakeholder is accounted for and included, and everyone that isn’t is scrutinized if they insist on being involved without a clear logical explanation.
There are many difficulties in driving a custom silicon project that only common sense, people management, determination, technical competency in the systems and silicon domains, and a solid process can overcome so that you can go from concept to mass production with confidence. I hope this short list above is a helpful first step for you.
CustomSilicon.comis the leading consulting firm in the custom silicon strategy and project management space for AR/VR, automotive, mobile, server, crypto, sensors, security, medical, space and more.
Raul has 20 years of combined experience in the system electronics and silicon industries. He is currently responsible for major system company’s custom silicon and sensor projects with projects approaching 30 total chips. Raul was the directly responsible silicon manager for 18 chips ramped to mass production at Apple for iPhone and iPad, and 23 total chips ramped to mass production counting projects where he was an expert reviewer. Raul was directly responsible for the development of mobile processor System PMICs for the iPad2, New iPad, iPad mini, iPad 4 and iPhone 5s. Other silicon included, backlight/display power for iPhone 5 and iPhone 5s, lightning connector silicon and video buffers. He managed supplier teams across the Globe.
Our network of experts provide our clients with an A+ silicon management team from day one.
System-level expertise, once the domain a few architecture specialists, is now shouldering its way everywhere into chip design and verification. In virtual modeling together with OS and application software certainly. That now couples into mixed-level system-verification, using different levels of abstraction for different parts of the system. In architecture analysis for major components, connecting to frameworks especially for AI. For hardware and software partitioning and experimenting with memory architectures. Verifying your architectural model against extensive test suites. And finally synthesizing the design to RTL while experimenting with further micro-architectural performance and power choices. You need more ESL expertise for non-experts.
When ESL becomes essential but is not a core-expertise
At one time ESL was dismissed as a fringe concept, interesting primarily to academics and super-early adopters. However, AI and the sheer size of AI test databases has put that idea to rest. If you want to do more than simply drop your trained DNN on an AI accelerator, especially if you want to experiment with memory optimization, you’re going to have to go through some kind of ESL path. If you want to verify image recognition test suites on the design, you have to do that in ESL. Attempting this at RTL would be insanely slow. And if you have to be competitive in performance and power, you have to optimize at the micro-architectural level. Fiddling with clock gating isn’t going to get you there.
The challenge for many of us is that while we have teams of smart people, they’re expert in RTL, not ESL. Now they have to learn about TensorFlow, PyTorch and other strange frameworks. And they have to learn about ESL. They’re smart, they’ll get there but is there any way you can speed up that learning curve? That’s the goal of CircuitSutra. They’re a consulting organization providing assistance in accelerating adoption of ESL methodologies for active design teams.
Endorsements
They’ve already proven their worth in projects at LG, TI and GreenSocs, among others. One endorsement was for the company developing the TLM Kit and sockets for a proprietary SoC bus. The kit they built is compliant with Accellera TLM2.0 and was used to develop the SystemC models of peripheral IP. Even better, the kit relieves the model developer from the complexity of TLM rules for modeling data communication at different abstraction levels. These range from loosely timed to cycle accurate TLM, with very simple-to-use abstraction-independent APIs. The level of abstraction can be changed at run time, allowing the modeler to dynamically adjust the performance accuracy trade-off, for instance, to support “fast-forwarding”. CircuitSutra came up with an innovative design that is extensible and can be easily adapted for any SoC bus architecture. They also developed a very comprehensive test-suite and ensured high functional coverage.
Another mentioned that CircuitSutra have successfully executed several modeling projects for their SoC bus architecture, Virtual Platform development, Integrating Virtual platform with the debugger and other tools, OS bring up on the virtual platform, SystemC Models of Image processing IP, Audio IP and OS bringup on VP. They particularly called out CircuitSutra as having strong expertise in modeling domain.
Also, very topical, they’ve added ESL expertise around RISC-V. Sounds like a company you should get to know.
You can learn more about the company in this video. And you can learn more about CircuitSutra HERE.
It should come as no surprise that S2C would step out in front with a high-density FPGA prototyping hardware platform for users who would like to scale to large numbers of FPGAs and high performance. That’s exactly what they have done with their new Prodigy Logic Matrix family of FPGA prototyping products that S2C announced in December. S2C has been in the FPGA prototyping business now for over almost two decades and has been a leader in high-quality hardware and complete solutions FPGA prototyping. Other large EDA suppliers have FPGA prototyping systems that support large numbers of FPGAs, but they’re encumbered by the supplier’s own ideas about optimal FPGA connectivity and compatibility with their other proprietary EDA tools such as emulation – often with a cost of lower prototyping performance. S2C’s new Logic Matrix family is architected for maximum flexibility without presumptions about FPGA interconnect or design flow – just an unencumbering assumption that the user may have their own innovative ideas about optimal FPGA interconnect to achieve the highest prototyping performance and utility.
Prodigy Logic Matrix
Each Logic Matrix comes with 8 FPGAs and is easily mounted in a 42U server rack – and up to 8 Logic Matrix may be loaded into a single standard server rack supporting up to 64 FPGAs per rack. Scaling to even more FPGAs may be accomplished by connecting multiple server racks – a project for seasoned FPGA prototyping veterans with a vision for prototyping multi-billion gate chip designs. The Logic Matrix LX1 is available now and sports the relatively mature Xilinx Virtex UltraScale VU440 FPGAs with an estimated prototyping capacity of 240 million usable ASIC gates. The Logic Matrix LX2 will follow in Q2 of 2021 and will use the newer Xilinx UltraScale+ VU19P, upping the estimated prototyping capacity to 392 million usable ASIC gates.
The Logic Matrix board format is open with plenty of connectors for all levels of interconnect – FPGA to FPGA on each Logic Matrix, Logic Matrix to Logic Matrix within a server rack, and rack to rack connections. The 8 FPGAs are surrounded by high-pin count Samtec connectors for single ended I/O or LVDS pairs (64 connectors), high-performance Samtec connectors (8 connectors), and mini-SAS connectors (80 connectors).
Sc2 EDA Logix MatrixS2C also made mention in the Logic Matrix family announcement of two other pieces of their high-density prototyping solution that are “soon to be released” – RTL partitioning and what S2C calls hierarchical connectivity to address local, Logic Matrix-to-Logic Matrix and rack-to-rack interconnect.
S2C’s other prototyping productivity tools may be paired with the Logic Matrix, including ProtoBridge and the MDM Debug Module. ProtoBridge is a PCIe to AXI interface between the FPGA prototype and a host PC for stimulating the prototype with high-speed (1GB/s) software-modeled transactions, video streams, or other streams of stimulus.
MDM is S2C’s multi-FPGA Debug Module that offers multi-FPGA signal viewing in a single viewing window. MDM comes with external hardware that provides 8GB of trace waveform storage without consuming user memory.
To round out S2C’s complete prototyping solutions with Logic Matrix, S2C offers a rich library of what it calls Prototype Ready IP – Daughter Cards that plug-and-play with the Logic Matrix to speed the creation of the prototyping environment around the FPGA prototype.
S2C is a worldwide leader of FPGA prototyping solutions for today’s innovative designs. S2C was founded in 2003 by a group of Silicon Valley veterans with extensive knowledge in ASIC emulation, FPGA prototyping, and SoC validation technologies. The Company has been successfully delivering rapid SoC prototyping solutions since its inception. S2C provides:
Rapid FPGA-based prototyping hardware and automation software
Prototype Ready™ IP, interfaces and platforms
System-level design verification and acceleration tools
With over 400 customers and more than 2000 systems installed, S2C’s focus is on SoC/ASIC development to reduce the SoC design cycle. Its highly qualified engineering team and customer-centric sales force understands our users’ SoC development needs. S2C systems have been deployed by leaders in consumer electronics, communications, computing, image processing, data storage, research, defense, education, automotive, medical, design services, and silicon IP. S2C has offices and distributors around the globe including the US, UK, Israel, China, Taiwan, Korea and Japan.
