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The Latest in Dielectrics for Advanced Process Nodes

The Latest in Dielectrics for Advanced Process Nodes
by Tom Dillinger on 01-12-2021 at 6:00 am
Categories: Events, Foundries, Intel Foundry

new ILDs v2

Of the three types of materials used in microelectronics – i.e., semiconductors, metals, and dielectrics – the first two often get the most attention.  Yet, there is a pressing need for a rich variety of dielectric materials in device fabrication and interconnect isolation to satisfy the performance, power, and reliability constraints of current microelectronic products.  Indeed, advances in dielectrics have been at the heart of the continued scaling achieved in advanced nodes.  (High-k gate dielectrics, for example.)

Additionally, the chemical properties of dielectric materials are critical in many process steps, from their use as a patterned hard mask to serve as a protective etch barrier to their use as a sidewall spacer to enable selective epitaxial growth on exposed silicon.  Dielectric materials need to support a multitude of deposition techniques, from chemical vapor deposition for isotropic addition on the surface topography to spin-on dielectric coatings to fill trenches.

Research in new dielectric materials is crucial, to support aggressive power, performance, yield, and reliability targets.  At the recent IEDM conference, Intel presented two papers describing some of their research (and other contributions) into the introduction of new dielectrics, and an interesting approach toward the corresponding metal interconnect fabrication.  [1, 2]  This article summarizes the highlights of these presentations.

Background

As briefly mentioned above, dielectrics are required to satisfy a multitude of requirements:

  • device gate oxide

Traditional Dennard scaling of the SiO2 gate oxide tox, with dielectric constant k~3.9-4.0, reached a non-manufacturable limit over a decade ago.   (For each new process generation, the multiplier for tox is 1/S, where the scaling factor S>1.)

New high-k gate dielectrics were required, to maintain the gate-to-channel electric field, while ensuring a sufficiently thick oxide layer to be manufacturable – i.e., uniformity, low defect density, low leakage current, low trap density, high dielectric breakdown strength.  Common examples are SiON, HfO2, HfSiON, and Al2O3.

Devices in each new process are now quoted with an effective gate oxide thickness, using SiO2 as the reference:   k(high-k)/tox(high-k) = k(SiO2)/tox_effective.  For example, if the target scaled tox_effective ~3nm, a 16nm HfO2 gate oxide layer would be fabricated, helping to achieve the manufacturability goals listed above.

  • M-I-M capacitors

High-k dielectrics are also crucial to the fabrication of metal-insulator-metal (decoupling) capacitors in the back-end-of-line fabrication, as illustrated below. [3]

The goal is to provide a high capacitance per um**2 , with minimal impact to available global routing tracks.

  • interlayer dielectrics (ILDs) surrounding interconnects

In this case, low-k dielectric materials have been introduced to reduce the parasitic capacitance (and thus, the R*C time constant) of interconnects.  Prior to the mid-90s, deposited SiO2 was the prevalent ILD, subsequently replaced with alternative low-k oxides – e.g., carbon-doped oxides, such as SiCOH (aka, “Black Diamond”, a TM of Applied Materials). [4]

Ongoing R&D into these ILD materials has drive the dielectric constant to k~2.3, a marked improvement over SiO2.  Recently, air gap dielectrics (k=1, ideal) have been introduced into BEOL processing – more on air gaps shortly.

A concern is the structural integrity of these ILD materials, due to their greater porosity.  This is especially true for low-k ILDs at higher metal levels, due to the stress introduced by the thermal expansion differences between the silicon die, encapsulation material, and package – delamination issues of the BEOL metal layers is a known failure mechanism.

There are also (very thin layer) dielectrics needed in the metal stack to serve as copper diffusion barriers.  (The diffusivity of CU into high-porosity ILDs is high.)

  • etch stops/etch barriers

A hard mask dielectric is patterned on top of a material which is to be protected during a process etch step.  The HM needs to have a very low etch rate relative to the exposed material being removed.  In a subsequent etch step, the HM needs to have a very high etch rate to the surrounding materials (assuming the HM is not a “leave-behind” layer).

  • dielectric deposition

To date, the majority of dielectric deposition process steps provide an isotropic layer over the die surface topography, whether using a chemical vapor deposition or spin-on method.

In a self-aligned, double-patterning process, a subsequent anisotropic etch step is used to provide “sidewall spacers”, as illustrated in the figure below. [3]

These spacers offer a unique, controlled method for several key process steps:  definition of fins for FinFET devices;  adding a dielectric between gate and source/drain nodes (with the spacer serving as a HM for subsequent S/D epitaxial growth).

Recent research is focused on a novel selective deposition process, where dielectric materials are deposited on specific die surfaces only – more on this unique method shortly.

New ILDs

Intel reported results on alternative ILDs to the current SiCOH-based low-k materials, using boron carbides (BCH) and boron nitrides (BNH).  The figure below illustrates the dielectric constant versus Young’s Modulus for various ILD materials.  (Young’s Modulus, or the “Modulus of Elasticity”, is an indication of the deformity of a material when subjected to stress forces – a higher coefficient implies less deformation.)

Note that while the dielectric constant for SiCOH is indeed low, the material strength is poor – alternatives with comparable k and higher strength are attractive.

ILDs for Subtractive Etch Metals

There is also active research into alternative interconnect metals to Cu, specifically Ruthenium.  The prevalent method for fabricating Cu wires and vias uses the formation of dual damascene trenches, with initial barrier/seed layers prior to Cu deposition.  This is followed by chemical-mechanical polishing (CMP) for surface planarization.

The potential introduction of Ru as an interconnect metal has renewed interest in patterning using subtractive etch – a deposited metal layer is masked, then etched, as was the case for Aluminum wires used prior to the transition to Cu.  In this case, deposition of the ILD is done after metal patterning – a flowable dielectric is an attractive option for filling the (high-aspect ratio) volume between the wires.

Selective Dielectric Deposition

For advanced process nodes, as illustrated above, a self-aligned, dual patterning (SADP) step is pursued to enable an aggressive pitch of etched layers, as an alternative to the cost of multipatterning lithography/etch process sequences.  Clearly, a lot of process steps are required to implement SADP.

An attractive alternative would be to implement selective deposition of the dielectric material (e.g., as an etch barrier).  The Intel IEDM paper shared research results on a “bottom-up” area-selective atomic layer deposition approach.

The figure on the left below illustrates selective deposition processes of interest:  dielectric deposition on an exposed metal surface (capping layer), dielectric deposition for trench fill, and selective sidewall dielectric deposition.  The figure on the right shows dielectric deposition on an existing dielectric but not the adjacent metal.

 

The figure on the right illustrates an approach to selective deposition — the wafer is pre-treated with a material which preferentially forms self-assembled monolayers on a specific surface.  Subsequently, atomic layer deposition of the dielectric does not nucleate and grow on this pre-treated area.

One specific application of selective deposition is illustrated below.

The use of graphene as an (atomically-thin) capping layer for Cu interconnects has been shown to improve (reduce) Cu line resistivity, compared to current capping dielectrics.  (A 15% experimental reduction in Cu resistivity is shown — that’s a major improvement.)

There are challenges, to be sure – the deposition selectivity should be high and the defect density low.  Nevertheless, selective dielectric deposition holds great promise to reduce fabrication process complexity.

Air Gap Dielectrics

The optimum ILD dielectric constant is 1, associated with an air gap between interconnects.  Intel has previously described their process for fabrication of air gaps, as illustrated below. [5]  After (damascene) metal patterning, the dielectric between the metal lines is etched, a thin diffusion barrier is added, and the next layer ILD is deposited and planarized.

An example of the delay/energy benefits of air gap dielectrics is shown below – the (simulated) circuit example is a datapath multiplier.

Dual Metal Layer Thickness

At IEDM, Intel also presented results from R&D efforts to provide two metal line thicknesses for an interconnect layer.

This option allows unique selection of line R and C values that comprise the R*C time constant, for optimal “tuning” of wire delays.  A first-order Elmore delay model for an RC interconnect tree is illustrated below, with the resulting effective point-to-point R*C summation equation. [3]  Note the strong dependence of the delay on the initial wire R values.  A dual-metal thickness option would offer unique R and C combinations along the fanout paths.

The process flow for fabrication of metal thicknesses  a-only, b-only, a+b, and vias is depicted graphically and with TEMs in the figures below.  (The option for fabricating air gaps between the two metal thicknesses is also shown.)

Layer ‘a’ and the vias utilize a dual-damascene process flow, while layer ‘b’ is single-damascene, followed by CMP.  Note the depth and aspect ratio of the air gap is quite high, to minimize the coupling capacitance values between adjacent wires, regardless of their thickness.

The figures below illustrate calculated values and testsite measurements for Cwire and R*C time constant for various interconnect thickness configurations:   all b;  all a+b;  b alternating with a+b;  a+b alternating with b;  with and without air gap dielectrics.

(Note that there is still the requirement to model the wire thickness tolerances due to CMP removal variation due to local interconnect density ranges.)

An example from Intel where separate R and C optimizations might be useful is shown below.

For a register file, the R*C delay product is more impactful for the address decode and word-line drivers (in M4 and M3), whereas C optimization may be the focus for (local and global M2) bitline implementations.

Summary

The demands on dielectric materials are great, from low-k ILDs to high-k gate oxides.  Hard mask etch stops require differentiated etch chemistry to surrounding layers.  New selective dielectric deposition methods offer the potential for significant process cost savings.

Although perhaps less captivating than new semiconductor and metallization materials being pursued, investigations into improved dielectrics is crucial to the PPA, yield, and reliability roadmap for microelectronics.  At IEDM, Intel provided an update on the activity that they and other researchers are pursuing.  I would encourage you to review their presentations.

-chipguy

 

References

[1]  King, S., et al, “A Selectively Colorful yet Chilly Perspective on the Highs and Lows of Dielectric Materials for CMOS Nanoelectronics”, IEDM 2020, Paper 40.1

[2]  Lin, Kevin, et al, “Staggered Metallization with Air gaps for Independently Tuned Interconnect Resistance and Capacitance”, IEDM 2020, paper 32.5.

[3]  Dillinger, T., VLSI Design Methodology Development, Prentice-Hall, 2019.

[4]  https://svmi.com/service/low-k-films/

[5]  Fischer, K., et al, “Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing”, IEEE Intl. Interconnect Technology Conference, May, 2015.

[6]  Hashemi, F., et al, “Selective Deposition of Dielectrics:  Limits and Advantages of Alkanethiol Blocking Agents on Metal-Dielectric Patterns”, ACS Applied Materials and Interfaces, Nov 2016.

 

 

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Achronix Speedster7t Garners Best Practices Award for FPGA

Achronix Speedster7t Garners Best Practices Award for FPGA
by Tom Simon on 01-11-2021 at 10:00 am
Categories: Achronix, eFPGA

Frost and Sullivan 2020 Award Achronix

FPGAs have played an important role in the growth of key markets, including networking, storage, mobile devices, etc. They offer a unique set of capabilities that ASICs, CPUs and GPUs find hard to match. FPGAs are wire-speed, programmable integrated circuits that accelerate data and applications.  The ability to reprogram the devices, even once they are deployed in an application, provides optimal flexibility while still yielding best-in-class performance efficiencies.  Some of the leading applications in these fast-changing markets include AI/ML for data center, edge compute, Industry 4.0 and intelligence for automotive, video compression, storage- and network-based acceleration, security and virtualization.  FPGAs are poised to be instrumental in the successful deployment of these applications.  Achronix Speedster7t provides the fastest interfaces in the market for an FPGA with PCI-e Gen 5, 400GbE and GDDR6.  Connecting all of the internal functional blocks, like machine learning processors (MLP),

general purpose DSPs, FPGA fabric as well as the external I/O is Achronix’s groundbreaking network on chip (NoC) which exceeds 20Tbps of bi-directional bandwidth.   Unlike other FPGA vendors, Achronix goes one step further and provides its technology as IP for integration into custom ASICs.   With this in mind the industry research firm of Frost & Sullivan has looked at the players in the FPGA market and has awarded Achronix with their 2020 Best Practices Award for FPGA for the Data Center Industry.

Achronix Speedster7t Award

Frost & Sullivan has a well-defined methodology for assessing companies and their technology for their level of innovation. The Frost & Sullivan best practices research paper on Achronix outlines the criteria and process for this assessment. It comes down to more than just what is in the product; it includes how the company works with customers and the internal processes to ensure the best results. Frost & Sullivan breaks it down into two main areas, New Product Attributes and Customer Impact.

New Product Attributes includes matching customer needs, reliability, quality, positioning and design. Customer Impact covers price/performance value, customer purchase experience, customer ownership experience, customer service experience and brand equity. Frost & Sullivan has in-house expertise and also uses external industry experts to vet their rankings.

Achronix scored high because of many factors. The Frost & Sullivan paper provides background on the growth of Achronix and a summary of Achronix’s Speedster7t architecture. Achronix offers both discrete FPGA devices and  embedded FPGA (eFPGA) intellectual property used for the development of custom ASICs and/or chiplets.   Achronix offers a 2D network on chip (NoC) that frees up the FPGA fabric resources by providing point to point high speed data transfers within the FPGA fabric and to memory, network and serial interfaces. Speedster7t also comes with PCIe Gen5, 400Gb Ethernet and GDDR6 interfaces for high speed data operations. Frost & Sullivan  highlights the dedicated arithmetic units in the FPGA fabric that support AI/ML operations. These Machine Learning Processors (MLP) are useful for programming the massively parallel operations that are needed in AI/ML processing.

Frost & Sullivan also looked at corporate culture and processes to rank Achronix. All of the peripheral interfaces undergo rigorous qualification prior to inclusion in their products. They have adopted state of the art IP that offers the highest performance and quality. Achronix also has built their development environment using industry standard tools. This means that new customers will already be familiar with the flow. Achronix has also pioneered 24/7 support through an online support system that makes it easy for customers to get any needed answers.

Achronix partners with customers, sharing their product roadmap to get early feedback. Also, eFPGA customers get expert help on configuring resources to ensure their applications will work optimally and integrate with the other SoC components. These steps help ensure first time silicon success and future-proofing so customer products will have long product lifetimes.

These fast changing markets like 5G, Automotive, Edge Compute and Data Center and their associated applications such as AI/ML, video compression and storage- and network-based acceleration, security and virtualization combine to make exciting opportunities for FPGA-based designs. Achronix has spent the time to deliver innovations that set them apart from the other players. Frost & Sullivan offers comparative rankings of several FPGA vendors in their report. The full report is available for download at the Achronix website. It offers a good overview of the FPGA market and interesting specifics about Achronix and the Achronix Speedster7t.

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Webinar: Rescale is Providing an On-Ramp to the Hybrid Cloud for Chip Design

Webinar: Rescale is Providing an On-Ramp to the Hybrid Cloud for Chip Design
by Mike Gianfagna on 01-11-2021 at 6:00 am
Categories: Events, Rescale, Semiconductor Services

Webinar Rescale is Providing an On Ramp to the Hybrid Cloud for Chip Design

We all know that design complexity is increasing at a fast pace. There’s always more analysis to run on larger and larger volumes of data. During tapeout, these demands can grow by an order of magnitude. Successful design projects need to add huge amounts of CPU, memory and storage for short bursts of time during tapeout to meet their schedule and time-to-market imperatives. All this wreaks havoc with the predictability and long-lead time provisioning associated with on-premises data center operations. “Bursting” to the cloud is the perfect answer to this difficult problem but getting there efficiently and reliably can be a complex task.  Until now. Recale has developed a comprehensive solution to this problem and they explain their approach in a very informative webinar. If you want to learn how Rescale is providing an on-ramp to the hybrid cloud for chip design, read on.

This webinar was originally presented as part of the SemiWiki Webinar Series and the replay is now available from Rescale. A link is coming, but first let’s examine what you’ll see and learn by attending. The webinar presents the benefits of a hybrid cloud approach to empower design teams to accelerate time to market and reduce schedule risk. Rescale’s all new hybrid cloud platform is presented. The platform is built to seamlessly transition workloads to the cloud for increased scale and performance, while maintaining the highest level of security and efficiency.  

Before I get into more details, I want to offer a personal perspective on the topic of cloud-based IC design. Simply put, it’s not as easy as it seems. During my time at eSilicon, we pioneered a complete cloud-based environment for front-to-back IC design. As they say, the devil is in the details and we encountered our share of demons along the way. Run-time consistency between on-prem and cloud, data coherency and controlled and efficient provisioning are just some of the challenges. A platform to handle all this is something to look at very seriously if you are contemplating a hybrid cloud environment.

Jose Fernandez

The webinar begins with Jose Fernandez, Semiconductor and Electronics Partnerships, providing an overview of Rescale. The company has been around since 2011 and has built an impressive portfolio of partners, customers and deployed applications. The figure below summarizes some of this data. Jose goes on to discuss the challenges of IC design today and the rather full platform Rescale provides to address these challenges. The names listed in this section will be familiar to all; Rescale has quite a large reach.

Rescale at a glance
Jeff Critten

Next, Jeff Critten, Account Executive discusses how Rescale’s capabilities impact chip design. Jeff provides details about how the platform is configured and highlights ease of use. The specific workflows supported are detailed. Jeff then presents several customer use cases and success stories. This discussion provides a lot of detail about what the problem was, who had it and how it was addressed. There is a well-produced video embedded in the webinar from Gaon Chips about how they use Rescale and the hybrid cloud to address their design challenges. This video alone is worth the time to view the webinar. You’ll hear perspectives from employees and ecosystem partners.

Riaz Liyakath

Next, Riaz Liyakata, Solutions Architect takes you through a Mentor Calibre live demo. Before he gets into the Calibre DRC demo on the cloud, Riaz provides an overview of the EDA tools and cloud providers that are available on the Rescale platform. The list is very complete and very impressive. The Calibre demo covers all aspects of deploying a complex application in the cloud, including provisioning, data management and runtime support. This is a very complete demo and will give you a strong sense of the breadth of the Rescale platform.

Jose completes the webinar with a summary of Rescale’s core strengths and benefits. I don’t want to give too much of the webinar content away, but this phrase says a lot:

Rescale is easy and powerful EDA in the cloud

If you are contemplating the need to burst to the cloud for your next design project, you need to see this webinar. Rescale is providing an on-ramp to the hybrid cloud for chip design. You can access the webinar replay here.

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Car Wars 2021

Car Wars 2021
by Roger C. Lanctot on 01-10-2021 at 10:00 am
Categories: Automotive

Car Wars 2021

A strange narrative took hold in the U.S. at the end of 2020 that vehicle sales were in decline, that cars weren’t selling. The reality is something quite different. In spite of nearly two solid months of auto factory and dealership shutdowns, automotive sales surged back in 2020 – a phenomenon that manifested globally with regional variation.

It took a Herculean effort on the part of auto makers accommodating auto workers and new car dealers accommodating uneasy customers, but the industry facilitated a miraculous recovery. For most makers and dealers sales are percolating again. In fact, several car makers selling cars in North America ran short of larger vehicles such as SUVs, crossovers, and pickup trucks. Turns out, cars and light trucks are pretty essential for a lot of people.

If the COVID-19 pandemic were negatively impacting vehicle sales in a prolonged and predictable way I might agree with the gloom and doomers. In fact, forecaster LMC Automotive estimates the negative impact of the two-month COVID vehicle/production sales hiatus (in the U.S. and elsewhere around the globe) to be a 15.8% hit to 2019 production volumes – to 74.1M vehicles produced globally, down from 89M in 2019.

LMC expects a recovery to pre-COVID production volumes by 2022 with steady growth eventually pushing volume toward and beyond 100M units annually. So it looks like cars are going to be with us for a while.

The fact is that the onset of COVID-19 has scrambled the anti-car culture dialectic that society, as a whole, was steadily evolving toward a carless future. This week kicked off with a story in USA Today (sourced from LawnStarter.com) describing the 10 best cities to live without a car. This is not to be confused with Curbed’s report on the 14 best car-free cities.

The vision of carlessness was gathering steam prior to the arrival of COVID-19. We saw the rise of congestion charging in London and Stockholm, to discourage the introduction of vehicles from the suburbs into city centers. We also saw bans on diesel fueled vehicles in multiple German cities battling smog. And we saw cities such as Paris and New York introduce roadway “diets” to reduce the available travel lanes for cars in favor of pedestrians, bikes, and scooters.

Further, we saw multiple countries – primarily but not only in Europe – pronounce end dates for the sale of internal combustion-based vehicles within 10 or 15 years. But flying in the face of these sanctions on individual vehicle ownership and operation, COVID-19 has directly and negatively impacted demand for mass transit – due to lockdowns and rider reluctance.

Consumers are increasingly opting for cars in a manner that is disrupting what was once a subtle and orderly transition away from cars. In the pre-COVID times cities were discouraging the creation of additional parking with new apartment and office construction. Clever policy makers were shifting the emphasis away from requiring sufficient parking in favor of a focus on public or ad hoc transportation options.

Now comes the report – also this week – from The New York Times that growing individual car ownership is making it increasingly difficult to find parking in New York’s residential neighborhoods. What this story misses is the reality that COVID-19’s impact is more complex than simply stimulating demand for individually owned and operated vehicles as consumers turn away from declining mass transit options.

The New York Times is right, though, to zero in on parking as the key pain point in shifting consumer transportation preferences. Indeed, parking is at the heart of the private car ownership “crisis” – if I may call it that. While the still fledgling transition to electric vehicles has introduced range anxiety, parking anxiety has always been and always will be a controlling factor for individually owned and operated vehicles.

Hans-Hendrik Puvogel, chief operating officer for Parkopedia, notes that the impact on parking is not really the old (and incorrect) 30% of traffic results from drivers driving around seeking parking spaces, but rather a shift in terms of usage patterns of parking assets.

“Residential parking is much more in demand than before. Street parking is in process of getting re-purposed for pickup/drop-off points, bike lanes, and loading zones. So, other off-street assets become very interesting (hotel and office parking and long-term parking in commercial parking garages).

“On the other hand, transient parking needs will decrease, as people stay at home, work from home, shop from home. In the short term that is going to create a mess in terms of parking and traffic, as the parking infrastructure is still geared for the old pre-Covid times, but eventually we will see a transformation of parking in the city centers.”

In response to this new reality, some expect shared robotaxis to replace privately owned vehicles. Don’t count on it. Sunny cities like Phoenix or tech hubs like San Francisco – will become increasingly overrun with robotaxis and will be forced to turn to road use tolling as in Singapore, Puvogel says.

Brutal economics will determine whether already deeply indebted robotaxi operators will be able to maintain fleets of driverless vehicles in constant motion when not charging. Cities are likely to have a low tolerance for these operators further tying up already clogged streets.

The policy implications for the car removers, with their road diets and reduced parking requirements for new construction, will be a forced rethink. Ample public parking and charging (for EVs) will be necessary to accommodate the growing flock of privately owned vehicles during a prolonged period of COVID-19 recovery during which mass transit will need to build back operations and rider confidence.

In the meantime, parking anxiety will become increasingly pronounced and companies, like Parkopedia, with solutions for locating the closest and cheapest parking spaces will thrive. The Car Wars of 2021 will be a battle for open parking spaces and available and compatible EV charging locations. Car-less living will simply have to wait for another decade or two.

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The Complexities of the Resolution Limits of Advanced Lithography

The Complexities of the Resolution Limits of Advanced Lithography
by Fred Chen on 01-10-2021 at 6:00 am
Categories: Lithography
4 Comments

The Complexities of the Resolution Limits of Advanced Lithography

For advanced lithography used to shrink semiconductor device features according to Moore’s Law, resolution limits are an obvious consideration. It is often perceived that the resolution limit is simply derived from a well-defined equation, but nothing can be further from the truth.

Optical Lithography: the fine print of the Abbe criterion

The “brick wall” resolution limit of an optical lithography system is the Abbe criterion recited as a formula: minimum half-pitch = 0.25 wavelength/(numerical aperture) [1]. In reality, though, the resolution limit is actually far more complex – it depends on the illumination direction. For on-axis illumination, with light only at the center of the pupil, the minimum pitch is wavelength/(numerical aperture). For lines in the plane of incidence, an incident angle corresponding to the numerical aperture (the maximum angle) in the wafer plane produces no image, whereas the same angle in the plane of incidence perpendicular to the lines gives a minimum pitch of 0.5 wavelength/(numerical aperture); this is the origin of the recited Abbe formula.

Post-optical lithography, such as EUV (extreme ultraviolet) and electron-beam lithography, is subject to several additional constraints on resolution.

Secondary electrons

As ionizing radiation, EUV, X-rays, electron beams, and ion beams all produce secondary electrons released from atoms. These electrons then move around, blurring the image. 15 nm half-pitch zones by electron-beam exposure of PMMA required double patterning, even for a 6.5 nm diameter 100keV electron beam [2]. Nanoimprint templates with 14 nm half-pitch also required double patterning using spacers [3]. Low-energy electron exposures indicate 20 nm thick resist may be patterned even with 2 eV electrons [4]. Thus, we expect secondary electron range to reach 20 nm, especially with higher doses. These higher doses are necessary to address stochastic defects.

Stochastic defects

Stochastic defects have recently been observed with some EUV studies[5,6]. It is believed to be generally applicable when shot noise affects the resist exposure, i.e., dose is too low. Thus, electron beam lithography is also likely to experience shot noise and stochastic defects [7]. Optical lithography doses, on the other hand, are generally well over the levels where shot noise would be a concern. Secondary electrons also can contribute to stochastic defects [8,9]. In relatively high volume, 5nm (5LPE) layouts are susceptible to stochastic defects [10]; these are expected to be 36 nm metal pitch (18 nm half-pitch) [11].

EUV thick mask effects

EUV specifically uses optically thick reflective multilayer masks, i.e., the 13.2-13.8 nm wavelength range light passes through a series of 80 alternating Si/Mo layers extending over many wavelengths. For a given angle of incidence q, the path covered by reflection from a given depth in the multilayer is proportional to cos(q). In radians, q can be expressed as 0.105 (1+a), with 0.105 representing the 6 degree central ray angle and a<<1. cos(q) can then be estimated by the Taylor approximation as 0.01 (1+0.5 a). It turns out a is inversely proportional to line pitch, for the optimum illumination (sine(angle) = 1/2 wavelength/ pitch). As a result, the phase difference between the 0th (a=0) and 1st (a=1/8 wavelength/pitch) orders used to form the image will increase dramatically as pitch decreases (lines perpendicular to plane of incidence), as shown in Figure 1 [12]. This phase difference has two detrimental effects: (1) best focus dependence on pitch, and (2) loss of image contrast (less sharp edge) at smaller pitches. Referring to Figure 1, restricting the phase difference to less than 30 degrees entails a pitch greater than 38 nm.

Figure 1. Phase difference between 0th and 1st orders for EUV illumination (sigma=0.5, 13.5 nm). Source: Reference 12.

So nothing comes easy

For the reasons above, it would be no surprise that double patterning would be used with EUV for ~30 nm pitch [13] and probably should be for ~40 nm pitch [14] as well. Active area (fin) pitches, which are already sub-30 nm, will be patterned by SAQP [15]. The table below summarizes the currently shown resolution limits of advanced lithography techniques used today.

References

[1] A. Yen, J. Micro/Nanolith. MEMS MOEMS 19, 040501 (2020).

[2] W. Chao etc al., Nature Lett. 435, 1210 (2005).

[3] T. Kono et al., Proc. SPIE 10958, 109580H (2019).

[4] I. Bespalov et al., ACS Appl. Mater. Interfaces 12, 9881 (2020).

[5] J. Church et al., J. Micro/Nanolith. MEMS MOEMS 19, 034001 (2020).

[6] P. de Bisschop and E. Hendrickx, Proc. SPIE 11323, 113230J (2020).

[7] P. Kruit and S. Steenbrink, J. Vac. Sci. Tech. B 23, 3033 (2005).

[8] H. Fukuda, Proc. SPIE 10957, 109570G (2019).

[9] H. Fukuda, Proc. SPIE 11323, 113230H (2020).

[10] J. Kim et al., Proc. SPIE 11328, 113280I (2020).

[11] https://fuse.wikichip.org/news/2823/samsung-5-nm-and-4-nm-update/

[12] A. Erdmann, P. Evanschitzky, and T. Fuhner, Proc. SPIE 7271, 72711E (2009).

[13] R. Socha, Proc. SPIE 11328, 113280V (2020).

[14] D. De Simone and G. Vandenberghe, Proc. SPIE 10957, 109570Q (2019).

Podcast EP2: Moore’s Law, Dead or Alive?

Podcast EP2: Moore’s Law, Dead or Alive?
by Daniel Nenni on 01-08-2021 at 10:00 am
6 Comments

Dan and Mike are joined by Dr. Walden Rhines for a scenic tour of Moore’s Law. The genesis and evolution of Moore’s Law are discussed, along with the fundamental processes that have driven it. How the technology world continues to grow and innovate in spite of a slowing of Moore’s Law is a central theme of the discussion.

Wally Rhines is widely recognized as an expert in business value creation and technology for the semiconductor and electronic design automation (EDA) industries. https://en.wikipedia.org/wiki/Wally_Rhines

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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IEDM 2020 – Imec Plenary talk

IEDM 2020 – Imec Plenary talk
by Scotten Jones on 01-08-2021 at 6:00 am
Categories: Events, Semiconductor Services, TechInsights

Imec Figure 1

On Monday morning at IEDM, Sri Samavedam of Imec opened the technical program with a plenary talk entitled “Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips”. I am not generally a fan of plenary talks, I think the presenters often try to cover too much in their talks and end up not providing enough detail to be useful, but there was a lot of good content in this talk.

I asked Imec for the slides to include some of them in this article, but they declined to provide them although they did send me the paper. I find it strange that they will not provide the slides, the video presentation of the slides is on the IEDM web site for registered attendees to view and anyone with a screen capture utility can easily capture any or all the slides. I will make use of a couple of the figures from the paper to try to make up for the lack of the slides.

The first approximately seven minutes of the talk were justifying the need for continued development of leading-edge technology and some historical perspective, I am going to omit this part as I believe the average Semiwiki reader and IEDM participant understand this already.

EUV Patterning

The talk then jumped into an EUV patterning roadmap. The presenter stated he thought High-NA EUV will be available for path finding around 2023 and will need two to three years to be ready for production. This would result in High-NA EUV entering production in the 2025/2026 timeframe, significantly later than I would have expected.

The Imec roadmap is for 3nm logic nodes to have 44-48nm Contacted Poly Pitch (CPP) and 21-24nm Minimum Metal Pitches (MMP), the 2nm logic node to be 40-44nm CPP and 18-21nm MMP and the 1.5nm logic node to be 40-44nm CPP, and 18-21nm MMP. I expect TSMC to be make risk starts with a 3nm node in late 2021 and production in 2022 and the CPP and MMP to be in the range of the numbers Imec proposes. I expect TSMC’s 2nm node to make risk starts in 2023 and production in 2024 and once again to have CPP and MMP values in the range that Imec presented. For 1.5nm Imec does not show any reduction in CPP and MMP ranges presumably reflecting a change to stacked transistors (more on this later) as a technique to drive density.

The Imec roadmap shows the current 0.33NA EUV systems being used for 3nm and 2nm and High-NA (0.55NA) being introduced at the 1.5nm node, this is once again later than I expected. I have for some time expected High-NA EUV to miss the 3nm node (although others have discussed high-NA for 3nm), but I thought the systems would be available for 2nm. If High-NA EUV systems are not available until 1.5nm it would be strictly as a cost reduction technique since 1.5nm has the same pitches as 2nm, and 2nm would already have been in production. Several years ago, I gave a presentation to ASML and raised the idea that by the time High-NA EUV was available transistor stacking (CFETs) might make it irrelevant. While it is likely that High-NA EUV can provide a cost reduction versus multi-patterning with EUV, if this timeline is correct it will not be a technology enabler.

I reached out to ASML for a comment on this and got the following reply:

“We are aligning with customers on roadmap timing of High NA insertion in volume production, currently estimated to be in the 2025-2026 timeframe. We will work with them to ramp to HVM as quickly as possible. Looking back at prior transitions, like ArFi, usually it takes a couple of years to ramp to HVM after first tool shipments. So a 2025-2026 HVM timing would help our customers reduce use of EUV multiple patterning and provide benefits in cost, process complexity, and cycle time.”

Logic Scaling

One of my favorite slides in the presentation is the Logic Scaling Roadmap slide and thankfully it is a figure in the paper (see figure 1.)

Figure 1. Logic Scaling Roadmap

For the 3nm node Imec shows a 5-track height cell based on a FinFET, this is the approach that I believe TSMC is taking. Samsung on the other hand has announced they will use Gate All Around at 3nm (a Horizontal Nano Sheet, HNS) and I believe this will be a 6-track height cell because to get to 5-tracks with HNS requires Buried Power Rails (BPR) and BPR is not ready for production yet (Samsung 3nm will be significantly less dense than TSMC 3nm based on the companies announced density improvements).

At 2nm, 5-track HNS utilizing BPR is an option or even HNS with a Fork Sheet (FS) to enable a less than 5-track cell (Authors note: ~4.33-tracks may be possible by combining HNS, BPR and FS).

Moving forward to 1.5nm CFETs with nFET and pFET stacking and 4-track cells can provide a shrink while maintaining the same pitches as 2nm. Imec is doing a lot of research on CFETs, Intel presented an interesting paper on CFETs at the conference that utilized three pFETs and two nFETs in a stack to match the performance of the two device types, and Synopsys also presented on CFETs in a paper that I was a coauthor on.

For 1nm and beyond Imec is working on 2D atomic channels and less than 4-track cells. There is also work that I am aware of to further extend CFETs by stacking more layers. 2D atomic channels would be stacked up like nanosheets but due to the extremely thin layers potentially provide higher frequency performance at the same power.

The presentation went on to further discuss BPR. BPR can lower the power delivery resistance improving power efficiency and provide an area reduction by creating tall metal lines in the substrate to replace wide metal lines in the interconnect layers. BPR can also enable power delivery networks on the back of a wafer that connect to BPR by using through silicon vias (TSV) although this requires very small “nano” TSVs. Utilizing the backside of the wafer for power delivery would also enable Metal Insulator Metal (MIM) Capacitors and Electrostatic Discharge (ESD) protection diodes to be integrated on the backside.

Beyond 2D atomic channel transistors, Imec is investigating various option including Qubits for quantum computing.

BEOL Roadmap

Looking at the Back End of Line (BEOL) Imec believes copper dual damascene can scale to a 21nm pitch but via resistance will be a problem. To address via resistance a hybrid scheme is needed where the vias are fabricated with an alternative material such as ruthenium, molybdenum, or tungsten. 3nm node processes are defined in the Imec roadmap as having pitches of 21-24nm so standard dual damascene copper is probably OK for the 3nm node. In the Imec roadmap the 2nm node has 18-21nm metal pitches so hybrid metallization will likely be required for the most critical layers.

Beyond 21nm pitch, subtractive metal patterning becomes attractive to enable high aspect ratio metal lines with partial or full air gaps to address line to line capacitance. Because copper is so hard to dry etch, subtractive metallization will require new metals such as Ruthenium or Molybdenum. The combination of Semi Damascene (with subtractive patterning) and air gaps results in a significant reduction in the resistance-capacitance (RC) of the interconnect. Imec has demonstrated 32nm pitch and is currently working on 18nm pitch. The initial 18nm results show better RC performance but still need work on self-aligned vias and air gap fabrication. Semi Damascene is a candidate for the 1.5nm node.

Beyond the 1.5nm node Imec is investigating alternative materials. The figure of merit for materials at very small dimensions is the bulk resistivity multiplied by the electron mean free path, this is because at small dimensions materials with long electron mean free paths, see a significant increase in resistivity. Imec has identified several promising alloys in simulations and needs to work through the integration challenges and demonstrate the materials are viable on actual devices.

SRAM Scaling

Continued logic scaling has been enabled by design technology co-optimization enabling track height reductions but this does not carry over to SRAM cells. Where SRAM cell sizes once scaled at 50% per node that scaling has slowed. A move to HNS will provide some gate length scaling but limitations on sheet width will limit scaling. FS can provide a scaling boost and CFETs can offer additional reductions.

There are also opportunities to utilize sequential 3D integration schemes and fabricate logic over SRAM arrays on pre-processed wafers, but this technique would require low temperature processing of the logic without compromising performance.

Deconstructed Chips

Increasingly capable 3D integration schemes offer the ability to deconstruct chips into multiple chips with each chip optimized for its function. Breaking up a complex system on chip (SOC) design into chiplets would allow optimized chiplets, for example one chiplet could be a processor core, other chiplets could be SRAM cache lower-level cache, MRAM or DRAM for higher levels cache or main memory all integrated with very high band width. Specialty devices fabricated with compound semiconductors could also be integrated. In order to realize the full potential of deconstructed 3D integration improvements in wafer to wafer bonding, micro bumps and power dissipation challenges need to be overcome.

Figure 2. illustrates Imec’s view of the 3D integration landscape.

Figure 2. 3D Integration Landscape.

 Conclusion

The technologies discussed here offer ten to fifteen more years of logic scaling. EUV patterning with the 0.33NA to High-NA (0.55NA) transition, HNS, FS, BPR, PDN, CFETs and 2D atomic channels, new SRAM scaling techniques and 3D Integration are all promising candidates for future logic technologies.

Also Read:

No Intel and Samsung are not passing TSMC

Leading Edge Foundry Wafer Prices

VLSI Symposium 2020 – Imec Monolithic CFET

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The Growing Chasm in Electronic System Design

The Growing Chasm in Electronic System Design
by Rahul Razdan on 01-07-2021 at 10:00 am
Categories: EDA

supply chain block diagram

Since the formation of the Electronic Design Automation (EDA) industry in the 1970s, Moore’s law has increased functionality onto a semiconductor die dramatically.  In response,  EDA tools for semiconductor design have also grown in functionality and the design processes for semiconductors have moved forward at a breakneck pace. Interestingly, during the same timeframe, board design has largely stayed stagnant. Many of the major platforms for PCB design are decades old with specific additions in areas such as high-speed interconnect and advanced packaging.

Observation one: For the vast majority of system designers, PCB design today is not too dissimilar from the design process from the 1980s. 

Further, there is a large and growing chasm for system designers between consumer and non-consumer products. Consumer markets drive the level of volume which is very interesting for semiconductor companies. To support the consumer markets, semiconductor companies provide focused application resources and in some rare cases will even build custom silicon for the system provider.  However, the vast majority of system designers in very important markets (energy, defense, aerospace, and industrial) face an environment which is still dominated by the age old manual datasheet. The only real computer aid is the PDF textual search. Beyond the data sheet, the various important EDA artifacts of the chip such as mechanical structure, pinout, software drivers are disaggregated across vendors (often connected to EDA tool libraries) and must be chased down.  Overall, it is a very manual, tedious, and error prone process.

The major players in the semiconductor ecosystem (figure above) certainly have a desire to help their customers, and  there is an attempt to help system level designers with various capabilities.  These include:

  • Reference Designs:  Semiconductor vendors publish reference designs on their websites focused on communicating the proper way to use their chips.
  • Application Notes:  Semiconductor and other players often write application notes which discuss the applicability of electronics systems in particular vertical markets.

Observation 2:  There is a sea of information available on the internet, but it is distributed on a variety of websites in various non-standard ways. The only real automation mechanism available to a system designer is google search.  However, a generic textual search engine has its limitations in a semantically rich environment such as electronics system design.

Aggregators such as distributors certainly have made an effort to service system designers in the part selection process. Vendors such as Digikey and Mouser provide some insights on the availability of parts based on high level selection of hardware functionality on their websites.

Observation 3:  The part selection process is focused on semiconductor chips, so it does not provide clarity on the ability of other methods of implementing the same function. These might include sub functions in larger SoCs, programmable fabrics, software emulation, and more. This is simply not the focus of distributors today.

In fact, the fundamental design factors for most system designers such as operating environment, the vertical market certifications, important ecosystems (ARM, x86, etc), and useful lifetime of product are not addressed in any existing EDA system today. This leaves designers with the unenviable task of wading gingerly into an ocean of disorganized information. Further,  semiconductor chip design has a deep capability which defines and enforces design rules through the implementation of automated checks by EDA tools. This ranges from layout DRC to logical assertions.  PCB design systems certainly have some concept of layout DRC, but the higher levels of checks surrounding logical connections do not exist in the system board design suite.

Overall, the lack of automation at the system design level has an impact on designer productivity as well as correctness, and this is becoming an increasing problem. Why?

AI/IOT mega-trend:  As “The Coming Evolution in Electronics Design Automation” describes, the next big mega-trend is the move of electronics to the edge with sensor, analog, DSP, and cloud connected systems. A key enablement of this paradigm is a highly productive design capability.

The millennial designer: While datasheets may be the preferred method of communication for seasoned designers, the newer generation of designers expect a much higher degree of automation.

In conclusion, with the current productivity of the system design process, the limiting factor for semiconductor growth in non-consumer markets will increasingly become designer bandwidth. Much like semiconductor EDA, there is a need to invest in system design EDA capability to unleash the power of electronics to solve important societal problems in fields ranging from defense to sustainability. 

Also Read:

The Coming Evolution in Electronics Design Automation

The Increasing Gaps in PLM Systems with Handling Electronics

The Increasing Gap between Semiconductor Companies and their Customers

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Conference: Embedded DevOps

Conference: Embedded DevOps
by Daniel Payne on 01-07-2021 at 6:00 am
Categories: EDA, Perforce

embedded devops min

The catchy phrase DevOps is defined by Agile advocates as, “The practice of operations and development engineers participating together in the entire service lifecycle, from design through the development process to production support.”

I’ve been developing software since the stone ages, which means that my first computer language in college was Fortran, and yes, we typed onto Hollerith cards and fed them into a Control Data card deck reader. A lot has changed since then, and I’ve since learned to code in many languages: BASIC, Fortran, Pascal, Assembly, C, ASP, Perl, Tcl/Tk, ColdFusion, PHP, HTML, Verilog, VHDL, Jquery, CSS, MySQL.

Perforce is well-known in the DevOps community, and they invited me to attend their upcoming webinar on February 4th, Embed DevOps, Summit 2021. So stay tuned for a detailed blog on one of the presentations. For now, let’s take a look at the three parallel tracks being offered:

  • Plan – Explore methodologies, tools, and practices that can help you cut costs in the planning stage of development.
  • Create – Learn how to improve things like collaboration, scaling, and versioning to reduce the time it takes to create a quality product.
  • Verify – Understand various practices that help you verify safety standards to reduce risk.

Plan

There are three sessions in this track that will help you explore methodologies, tools, and practices that can help you cut costs in the planning stage of development.

  • Scrum, Kanban, and Gantt Scheduling in One Project – Nonsense or Necessity?
  • Community vs. Enterprise Open Source – Which is Right for Your Business?
  • CWE Top 25: History, Tools and Techniques

Create

Four sessions are included in the Create track, which I plan on attending, and here you will learn how to improve things like collaboration, scaling, and versioning to reduce the time it takes to create a quality product.

  • Embedded Software Development at 5G Speed
  • Secure Collaboration in a Cloud-based Chip Design Environment
  • Optimizing Your CI Pipeline
  • Implementing a Unified HW/SW BoM to Reduce System Development

Verify

The third track has three presentations, and Verify will help you to understand various practices that help you verify safety standards to reduce risk.

  • CI Efficiency: How to Verify Every Developer Commit
  • Role of Coding Standards in Autonomous Vehicles
  • How to Improve Development with Strong Requirements Taxonomy

Presenters

Industry experts in each area will be at the virtual podium to bring us up to speed on embedded DevOps, and I’ve met two of them in real life: Vishal Moondhra of Methodics and Warren Savage, a researcher from the University of Maryland.

Summary

Mark your calendar for February 4th, then sign up early for the first virtual user conference from Perforce all about embedded DevOps. The conference is in good alignment with popular trends of: 5G, autonomous vehicles, cloud and open source software. As part of my continuous learning I’m looking forward to this conference next month, so why not join me.

Also Read:

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Technology Optimization for Magnetoresistive RAM (STT-MRAM)

Technology Optimization for Magnetoresistive RAM (STT-MRAM)
by Tom Dillinger on 01-06-2021 at 6:00 am
Categories: Foundries, GlobalFoundries
6 Comments

profile simulations

Spin-transfer torque magnetoresistive RAM (STT-MRAM) has emerged from several foundries as a very attractive IP option.  An introduction to MRAM technology from GLOBALFOUNDRIES was provided in this earlier SemiWiki article. [1]

Briefly, STT-MRAM is a non-volatile storage option with the following attractive characteristics

  • high storage duration
  • high density (one access transistor connected to a magnetic tunnel junction)
  • random access
  • near-zero leakage power
  • radiation-hard
  • high-performance write cycle (with low write bit error rate)

There are limitations with STT-MRAM that require detailed process engineering:

  • thermal sensitivity of the energy barrier that defines the spin-polarization stability (“the exchange stiffness”)

A key application area for embedded MRAM qualification is the automotive market, with its more demanding -40C to 150C temperature environment.

  • limited endurance cycles

MRAM IP is targeted to displace embedded flash at more advanced process nodes – in this case, limited endurance is sufficient.  For applications such as the last-level cache in high-performance SoCs, higher endurance is required.

The nature of the STT-MTJ requires unique modeling and micro-magnetic simulation techniques to optimize the selection of materials and physical dimensions.  At the recent IEDM conference, GLOBALFOUNDRIES provided a perspective on the optimization of their MRAM technology offering. [2] This article summarizes their presentation.

Introduction

The magnetic tunnel junction (MTJ) consists of multiple ultrathin layers of unique metal and oxide materials, as illustrated in the figure below.

 

Recall that a material demonstrates magnetization due to the spin and orbit of its electrons.

A “soft” magnetic material only contributes to the magnetic flux around the material when an external magnetic field is applied – when the field is removed, there is no remnant magnetization.

A “hard” material is always magnetized.  When an applied magnetic field in the opposite direction of the magnetization exceeds a critical value, the polarity of the magnetization reverses, and remains magnetized in this orientation when the applied field is removed.  The magnetostatic energy in the hard material may differ based on the direction of the magnetization – i.e., a preferred direction in the absence of an external field – known as the magnetic anisotropy.

The configuration shown in the figure above is a perpendicular MTJ.  The materials selected for the junction provide for a perpendicular magnetic anisotropy (PMA), which enables a stable, non-volatile “anti-parallel” magnetic state between the reference and free layers.

The figure below depicts the perpendicular TMJ interface between the magnetic layer and the oxide – note in the figure that an “in-plane magnetic anisotropy” device is also depicted, but does not contribute to the PMA.

The perpendicular MTJ is emerging as the preferred material stack, for the following characteristics:

  • the PMA energy is larger for the p-MTJ than the in-plane anisotropy, with better retention at smaller MTJ sizes
  • the critical current density through the MTJ area to switch the magnetization is less for the perpendicular junction
  • as a result, the MRAM bitcell density may be much higher

The TMJ consists of a “reference” magnetic layer separated from a “free” magnetic layer by an extremely thin oxide.  The free layer magnetization is switched between anti-parallel and parallel orientations to the reference layer, with a corresponding change in the junction electrical resistance (measured at low “read” current).  The tunneling magnetoresistance ratio (TMR) achieved between the AP and P states is a key process development parameter, as it directly influences the memory read sense behavior.

The unique nature of the STT-MRAM cell is the manner in which the free layer magnetization is altered.

The angular momentum (“spin”) of an electron is normally random – thus, a conventional electrical current is non-polarized (1/2 spin-up, 1/2 spin-down).

However, an electron current through the reference layer produces a spin-polarized current through the tunnel oxide to the free layer.  The angular momentum of this electron current can be transferred to the free layer electrons, due to “spin-transfer torque”.  If the junction current magnitude is sufficient, the magnetic polarization of the free layer can be switched to parallel, as mentioned earlier for the case of an applied external magnetic field.

An electron current flowing in the opposite direction from the metal electrode re-orients the free layer magnetization to its anti-parallel orientation.

The first figure above also included “synthetic anti-ferromagnetic” (SAF) and metal spacer layers, as part of the MTJ stack.  These additional layers help to increase the TMR ratio and improve the stability of the cell.

STT-MRAM DTCO

The GLOBALFOUNDRIES team provided an insightful view into STT-MRAM development, as summarized in the pyramid diagram above.

The first step (lowest pyramid level) in MRAM development is the stack engineering of materials – e.g., crystalline structure, atomic composition, thickness, and interface properties at each layer boundary.  Detailed “spin-polarized” calculations are used to determine the follow material characteristics described earlier:

  • magnetic anisotropy (K)
  • magnetic saturation in the material (Ms)
  • TMR

For example, the figure below illustrates a calculation of the “energy barrier” associated with the free layer interface to the neighboring oxide – as mentioned earlier, the perpendicular anisotropy is of interest (so the in-plane magnetization polarization energy is subtracted).  The free layer in this example is a Cobalt-Iron (CoFe) material, roughly 10Angstroms thick; the tunnel oxide is MgO.

Recall from the discussion above that an increase in the PMA offers greater cell thermal stability and data retention – the adjoining figure above illustrates how this energy barrier changes based on the Co(x)Fe(1-x) material composition in the free layer.

An additional material analysis relates to modeling the spin-polarized electron tunneling current through the MgO oxide layer, as illustrated below.

The next level of the DTCO pyramid is to extend these electron-level, “ground-state, zero K” material simulations to include the temperature dependence of:  the material magnetic saturation (Ms); the magnetic anisotropy (K); and, the STT exchange behavior.

The figure below depicts how these properties change with temperature.  The data enable process engineers to determine how the PMA stability energy barrier varies with temperature, and ultimately to define the bitcell write cycle current and duration requirements for the temperature range of interest.

Note that the figure also includes an analysis of a “magnetic defect density” in the polarized material.  During fabrication and assembly, a SoC containing an embedded MRAM will be subject to elevated annealing temperatures – e.g., a minimum of 260C for solder reflow.  There will be some degree of non-magnetic layer atomic diffusion into the magnetic material.

The next level of the DTCO pyramid introduced the MTJ physical dimension into the process development.  The figure below illustrates how magnetic “coupling fields” are present in a tapered, non-fully cylindrical MTJ after fabrication.

The figure above also depicts how the magnetic coupling field in the free layer is a function of the MTJ diameter and thickness.  This external coupling introduces a dimensional asymmetry in the overall free layer-oxide interface, complicating the modeling of the parallel/anti-parallel switching behavior.  A high field coupling at the periphery slows the write transition for either the P-to-AP or AP-to-P magnetization orientation.  A detailed analysis is required to optimize the MTJ dimensions – large enough to avoid coupling-impacted write transition errors, yet still achieving array density and switching power targets.

The final, top level of the DTCO pyramid is the abstraction of the previous analyses of materials, temperature-dependence, and MTJ dimensional analysis into a suitable “compact device model” useful for MRAM array designers to incorporate with the SPICE models for array decode, bitcell access transistor, write driver, and read sense devices.

The success of the final compact model generation is depicted in the figures below.  The first illustrates the (AP and P) DC resistance measured versus model for two different MTJ stack designs.  The second figure depicts the interdependence between the required write pulse magnitude and duration, again showing excellent agreement between the compact model and measured MRAM hardware.

As highlighted above, the profile of the overall MTJ alters the coupling field to the switching free layer.  The DTCO flow developed by GLOBALFOUNDRIES includes a statistical compact model, reflecting the process variation in the MTJ, and thus the coupling field.

The figure below illustrates the results of a Monte Carlo simulation analysis of the MRAM, using the compact model incorporating a statistical distribution of the coupling field.  Again, excellent agreement with measured hardware is shown, when simulating the overall write error rate (“WER”), for a 20nsec write pulse width.  (Note that when a short write pulse ends, there is a probabilistic measure that the free layer may “relax” back to its existing state, constituting a write error.)

As an experiment, an artificial statistical distribution (“B”) for the MTJ profile and resulting coupling field was simulated, showing the strong dependence between MTJ process variation and WER.  MRAM fabrication engineers are focused on improving the MTJ layer etch definition, to achieve better WER and correspondingly improved overall write cycle endurance.

Summary

GLOBALFOUNDRIES presented an extremely enlightening view into the complete DTCO flow for STT-MRAM development.  Material characteristics are analyzed across (ground state and high-temp) conditions, resulting in input parameters used at higher levels of model abstraction.  The influence of manufacturing variation – e.g., MTJ sidewall taper, material defect densities – were also incorporated into the overall model environment, due to the influence of coupling fields on MTJ behavior.  The resulting compact models used in a traditional circuit design flow demonstrated excellent agreement with experimental hardware data.

I would encourage you to seek out a copy of the IEDM presentation from GLOBALFOUNDRIES to gain insights into the DTCO steps involved in MRAM process engineering.

-chipguy

References

[1]  https://semiwiki.com/semiconductor-manufacturers/287266-embedded-mram-for-high-performance-applications/

[2] Dixit, H., et al, “TCAD Device Technology Co-Optimization Workflow for Manufacturable MRAM Technology”, IEDM 2020, paper 13.5.

Also Read:

3DIC Design, Implementation, and (especially) Test

Designing Smarter, not Smaller AI Chips with GLOBALFOUNDRIES

The Most Interesting CEO in Semiconductors!