SemiWiki – Page 220 – The Open Forum for Semiconductor Professionals

February 9, 2023April 10, 2023

The State of IC and ASIC Functional Verification

Way back in 2002 there was a study from Collett International Research on functional verification, and since 2010 the Wilson Research Group has continued that same kind of study with a new report every two years. What attracts me to this report is that it doesn’t just look at the installed base of one EDA vendor, instead it looks across the world asking questions of design and verification engineers, so that the rest of us in the semiconductor industry can understand what the trends are for functional verification.

Our global semiconductor market had a total value of $547 billion in 2021, dipping to $545 billion in 2023, then forecasted to grow to $635 billion in 2025, according to IBS, where the IC and ASIC segment would reach $330.9 billion in 2025. Systems designers using IC and ASIC components expect that functional verification has been thorough and correct, ensuring that their products operate properly and reliably.

980 engineers responded to the 2022 survey across the implementation spectrum of FPGA, IC, ASIC, full custom, structured custom, structured ASIC, to even include embedded array and gate array design styles. This blog focuses just on the IC and ASIC segments.

The very first metric in the report showed a sad result that first silicon success was moving downwards at only 24%, which means an expensive re-spin plus lost time to market for even more lost revenues.

# of IC and ASIC spins

The top five causes for these silicon re-spins in ranked order are:

Logic, functional
Analog
Power Consumption
Clocking
Yield

So functional flaws are the number one cause for failure, then this category is expanded to show us how design errors, changes in the specification and incorrect specification are the low-level culprits. IP vendors should note that both internal and external IP blocks contribute less to functional flaws than design errors.

Functional Flaws

Here’s a common question from management, “Is the project on schedule?” Not quite is the realistic answer, as 66% of IC and ASIC projects completed behind schedule.

Project Design Completion

The percentage of total time spent in functional verification has held pretty constant since 2008 at about 70%, while the mean peak number of both design and verification engineers has grown to about 12. Even design engineers are spending 49% of their time doing verification. Verification engineers spread their time doing five activities:

47% – Test planning
21% – Creating Test and Running Simulation
15% – Testbench Development
13% – Debug
5% – Other

IC and ASIC trends show that the number of embedded processor cores is increasing, as 74% have one or more cores, 52% include two or more cores, and 15% have eight or more cores. RISC-V processors were found n 30% of designs in 2022, up 23% from two years prior. AI accelerators were seen in 32% of designs. To manage power on SoC designs we see an increase in the number of clock domains, with 3-4 being the average number.

Asynchronous clock domains are predominant at 93% of designs, creating a need for more gate-level simulation and CDC verification tools. Security features are being added to 58% of IC/ASIC designs for things like encryption keys, DRM keys and handling sensitive data. Here’s the distribution for safety-critical standards:

Safety-critical Standards

FuSa (Functional Safety) project time was spent on four activities, taking less than 25% of project time: Safety Analysis, Safety Architecture and design, Safety requirements, Safety verification.

Verification languages and methodology are spread out across 10 categories, with SystemVerilog in top use, while Verilog use decreases, and Python is an emerging trend:

Verification Languages

Accellera UVM remains the most used verification methodology, and the Python-based cocotb was recently added this year.

Verification Methodologies

For assertion languages there is SystemVerilog Assertions still on top at 72%, with OVL at 15% and PSL at 9%. Formal property checking was used in 35% of designs, and automatic formal checking grew to 32% of designs, both categories grew quickly in the past 8 years.

There are four simulation-based techniques tracked in the survey, so no new approaches added in the past 15 years:

Simulation Techniques

Software-based verification is limited by speed and capacity issues, so hardware-based emulation and FPGA prototyping have arrived just in time to help verify the largest SoC devices by running actual software and operating systems. The top six reasons to use emulation or FPGA prototyping are listed with HW/SW co-design and verification as the most important factor.

Emulation and Prototyping

Emulation and prototyping have recently improved in capacity to exceed 1 billion gates, not counting memories.

Summary

Functional verification is essential to knowing that a new electronic design meets the specification, functions reliably and works properly on first silicon. Both design and verification engineers spend their time in functional verification using multiple languages, methodologies and even hardware-assisted platforms to reach their goals of on-time project delivery. This bi-annual report is rich with information to help our industry see the functional trends for IC and ASIC designers, then respond with best practices and keep engineers updated and trained on how to work smarter, not harder.

Read the complete 17 page report by requesting it online.

Stay tuned for a separate blog on FPGA functional verification trends.

Related Blogs

February 9, 2023July 18, 2025

Synopsys Design Space Optimization Hits a Milestone

Synopsys Design Space Optimization Hits a Milestone
by Bernard Murphy on 02-09-2023 at 6:00 am
Categories: AI, EDA, Synopsys

I talked recently with Stelios Diamantidis (Distinguished Architect, Head of Strategy, Autonomous Design Solutions) about Synopsys’ announcement on the 100^th customer tapeout using their DSO.ai solution. My concern on AI-related articles is in avoiding the hype that surrounds AI in general, and conversely the skepticism in reaction to that hype prompting some to dismiss all AI claims as snake oil. I was happy to hear Stelios laugh and agree whole-heartedly. We had a very grounded discussion on what DSO.ai can do today, what their reference customers see in the solution (based on what it can do today) and what he could tell me about the technology.

What DSO.ai does

DSO.ai couples with Fusion Compiler and IC Compiler II, which as Stelios was careful to emphasize means this is a block-level optimization solution; Full SoCs are not a target yet. This fits current design practices as Stelios said an important goal is fit easily into existing flows. The purpose of the technology is to enable implementation engineers, often a single engineer, to improve their productivity while also exploring a larger design space for a better PPA than might have been discoverable otherwise.

Synopsys announced the first tapeout in the summer of 2021 and have now announced 100 tapeouts. That speaks well for the demand for and effectiveness of a solution like this. Stelios added that the value becomes even more obvious for applications which must instantiate a block many times. Think of a many-core server, a GPU, or a network switch. Optimize a block once, instantiate many times – that can add up to a significant PPA improvement.

I asked if customers doing this are all working at 7nm and below. Surprisingly, there is active use all the way up to 40nm. One interesting example is a flash controller, a design which is not very performance sensitive but can run to tens to hundred of million units. Reducing size even by 5% here can have a big impact on margins.

What’s under the hood

DSO.ai is based on reinforcement learning, a hot topic these days but I promised no hype in this article. I asked Stelios to drill down a bit more though wasn’t surprised when he said he couldn’t reveal too much. What he could tell me was interesting enough. He made the point that in more general applications, one cycle through a training set (an epoch) assumes a fast (seconds to minutes) method to assess next possible steps, through gradient comparisons for example.

But serious block design can’t be optimized with quick estimates. Each trial must run through the full production flow, mapping to real manufacturing processes. Flows which can take hours to run. Part of the strategy for effective reinforcement learning given this constraint is parallelism. The rest is DSO.ai secret sauce. Certainly you can imagine that if that secret sauce can come up with effective refinements based on a given epoch, then parallelism will accelerate progress through the next epoch.

To that end, this capability really must run in a cloud to support parallelism. Private on-premises cloud is one option. Microsoft has announced that they are hosting DSO.ai on Azure, and ST report in the DSO.ai press release that they used this capability to optimize implementation of an Arm core. I imagine there could be some interesting debates around the pros and cons of running an optimization in a public cloud across say 1000 servers if the area reduction is worth it.

Customer feedback

Synopsys claims customers (including ST and SK Hynix in this announcement) are reporting 3x+ productivity increases, up to 25% lower total power and significant reduction in die size, all with reduced use of overall resources. Given what Stelios described, this sounds reasonable to me. The tool allows exploration of more points in the design state space within a given schedule than would be possible if that exploration were manual. As long as the search algorithm (the secret sauce) is effective, of

course that would find a better optimum than a manual search.

In short, neither AI hype nor snake oil. DSO.ai suggests AI is entering the mainstream as an credible engineering extension to existing flows. You can learn more from the press release and from this blog.

Also Read:

Webinar: Achieving Consistent RTL Power Accuracy

Synopsys Crosses $5 Billion Milestone!

Configurable Processors. The Why and How

February 8, 2023February 8, 2023

Cliosoft’s Smart Storage Strategy for Better Workspace Management

Cliosoft’s Smart Storage Strategy for Better Workspace Management
by Kalar Rajendiran on 02-08-2023 at 10:00 am
Categories: Cliosoft, EDA

Over the years storage has gotten very cheap, or has it? As a typical consumer, we take data storage for granted because access to it has gotten very cheap. Long gone are the days of being limited to 1.44MB floppy disks to store data. The smart devices we carry around with us can store 100’s of GB of data. That is a lot of data. But what about when we have to deal with data management when designing these very smart devices? The demand for data storage and management goes up orders of magnitude. Specifically, within the semiconductor realm, chip design data management is about terabytes and terabytes of data. It does not matter whether a company is using on-prem storage or cloud storage, the total cost of ownership (TCO) becomes an expensive proposition.

With teams of engineers accessing, adding, modifying and deleting data, the strategy for workspace management takes paramount importance. A smarter storage strategy is needed to enable efficient and cost-effective workspace management.

Pedro Pires from Cliosoft delivered an excellent webinar recently to address this very topic. Pedro is an application engineer and used Cliosoft’s SOS solution as the backdrop. His talk focused on minimizing design data storage consumption, fast workspace creation, and lightweight resource consumption.

Drawbacks of Traditional Approach to Workspace Storage Management

Many traditional solutions for data management simply make copies of the project data for as many users who are working on that project. While this may give the feeling of complete data control to every user, it is obviously a very storage inefficient approach. For example, if the project data size is 100GB and there are 10 users on the project, 1.1TB of storage is needed for starters. The bigger the project team, the more inefficient the storage solution becomes.

A better data management solution is preferable. And if that better solution can offer additional benefits on top of the storage efficiency, all the better.

Cliosoft SOS Solution for Workspace Storage Management

The Cliosoft SOS solution uses a three-pronged approach for very efficient project workspace storage management.

Links to Cache Feature

When the various users of a project create their workspace under the SOS solution, no physical copies of the project data are made. Instead, symbolic links are made to the actual physical copy that exists in the main repository. This automatically reduces the workspace footprint compared to the traditional data management solution discussed earlier.

When users want to work on particular views/files, they would checkout those files and SOS would automatically replace the relevant symbolic links with an actual copy of the views/files. Once the users work on these files and make necessary modifications, they can check those files back in. SOS will commit those changes to the physical copy in the main repository and replace the users’ physical copy with symbolic links again.

The cache repository keeps just a few revisions of all the data held in the main repository. This is a configurable aspect of the solution and the customer can select the number of revisions for the cache repository. But when it comes to the metadata contained in the main repository, the cache repository holds an exact copy of it. SOS keeps the metadata synchronized in real-time across all project sites, thus enabling all users to be looking at the same state of the project at any point in time.

Reference and Reuse Feature

Reuse of proven IP is very commonly practiced. That in itself is not a new concept. But how the proven IP is used from a data management perspective is what is new with the Cliosoft SOS solution. Instead of copying the various proven IP blocks for use in the project on hand, SOS makes references to these IP blocks. On top of storage space savings, the Reference and Reuse approach delivers IP trackability and traceability benefits as well. IP traceability is not only important but is a requirement when designing products in certain industries.

“Sparse Populate” Feature

The Sparse Populate feature takes the Links to Cache functionality of the SOS solution to the next level by further reducing the user workspace requirements. Invariably, in most projects, there are blocks of data, such as a library or PDK data that are only needed on a read-only basis. Instead of making symbolic links to each and every file within the library or PDK folder, the SOS solution creates a symbolic link to just the top-level of the directory structure.

When and as needed, SOS provides the ability for a user to switch from Sparse Populate setup to a fully-populated copy. When this switch is made, SOS replaces the top-level symbolic link with symbolic links to all the individual files within that directory structure. The user is able to make any changes to the required files and check back the updated files to the repository. Once done, the user can revert back to the Sparse Populate setup.

Summary

Cliosoft’s SOS solution allows customers to mix and match the functionality discussed above on a workspace by workspace basis. This offers flexibility for one user to use the Links to Cache functionality when another user may decide to use the physical copy approach. But for the conscious choice made, a user wouldn’t know the difference in terms of data access and performance as SOS automatically handles the operations. With the IP tracking and traceability functionality built into SOS, users can generate “who uses me” reports for various IP blocks to meet certain compliance requirements.

The entire webinar could be accessed here on-demand.

Also Read:

Designing a ColdADC ASIC For Detecting Neutrinos

Design to Layout Collaboration Mixed Signal

Agile SoC Design: How to Achieve a Practical Workflow

February 8, 2023March 15, 2023

ASIL B Certification on an Industry-Class Root of Trust IP

ASIL B Certification on an Industry-Class Root of Trust IP
by Bernard Murphy on 02-08-2023 at 6:00 am
Categories: Automotive, EDA, Security, Siemens EDA
1 Comment

I have always been curious about how Austemper-based safety methodologies (from Siemens EDA) compares with conventional safety flows. Siemens EDA together with Rambus recently released a white paper on getting a root of trust IP to ASIL B certification. This provides a revealing insight beyond the basics of fault simulation into a detailed campaign on an industrial scale IP. Siemens EDA and Rambus describe using the Austemper toolset on the on Rambus RT-640 root of trust IP, and the steps they went through to achieve functional safety metrics required for ASIL B certification.

The Austemper toolkit

In a typical FMEDA flow you would first use spreadsheets and engineering judgment to decide where you should insert safety mitigation techniques in an RTL design. Then you would run a fault campaign using fault simulation to determine how effectively your mitigation techniques have worked, as measured by the appropriate ASIL requirements. This could lead to lengthy loops to reach targets such as those for ASIL B.

In the Austemper flow, SafetyScope will estimate FIT rates and FMEDA metrics, and suggest a preliminary fault list before safety insertion. It can then be run again after fault simulation to provide a summary report with final metrics and detection coverage. Kaleidoscope runs fault simulation, categorizing faults as detected, not detected, not triggered, or not observed (at an observable point).

Faults modeled in the analysis

Following the standard, the Austemper flow models three types of faults:

Transient. These are as the name suggests temporary faults and may result from cosmic rays, electromagnetic interference, or other transitory stimuli. The flow runs a quick pseudo-synthesis to find state elements, putting these into the fault list. During analysis such a fault will be enabled at the outset then removed after some time window, remaining active until that point. The length of the window is configurable.

Permanent. These are durable faults and may result from design errors, configuration errors, deadlocks or other influences which can create a stuck state. Candidates include state and non-state elements and are modeled using stuck-at-1 or 0 values, just as in DFT analyses. These errors persist throughout a fault simulation.

Latent. These faults are very tricky to find and to mitigate because they result from a failure depending on two or more faults in the system, especially when one of them occurs in safety mitigation logic. Austemper models latent faults with one stuck-at in the functional logic and one in the corresponding safety system. (Latent faults depending on 3+ simultaneous failures have very low probability.)

Practical considerations in the fault campaign

Fault simulation of many faults over a large circuit could consume a huge amount of time without careful planning. The Siemens and Rambus guys suggested several techniques they used to keep this manageable.

First, they don’t always work with the full fault list. They strategically evaluate subsets of faults at different stages to slim down the set, before working on the hardest cases. For example, they analyze first around known safety-critical areas. Then they (temporarily) reduce the fault-tolerant time interval (FTTI) to determine faults which can be detected quickly. With similar intent, they temporarily treat sequential elements as observable points, allowing them to filter out any faults which reach a primary output without triggering an alarm.

This ultimately leaves them with a subset of undetected faults which must be analyzed for the full FTTI to determine if any escape to an output without raising an alarm. These are the most expensive to evaluate since they can fanout through multiple cycles, creating multiple simultaneously active faulty traces before ultimately registering as detected or otherwise.

Fault simulation depends on stimulus vector which may not trigger a fault, or may trigger it but not lead to it raising an alarm or being observed at a primary output. These faults they consider unclassified. Improving the stimulus may help but there are limits to that option for a software based and heavily parallelized software fault simulation. They suggest a couple of options to reduce the number of unclassified faults. In bus simplification, they assert that if a fault in one bit is detected, then all bits get the same classification. They make a similar assertion for duplicated instances of a module. If all faults within one instance are successfully classified, then all instances in other instances are also deemed classified. Finally they set an empirical threshold for the number of stimuli against which they test. A level at which they feel they tried “hard enough”. Arbitrary yes, but I don’t know how I would do any better.

Nice paper. You can read it HERE.

Also Read:

The State of IC and ASIC Functional Verification

ASIL B Certification on an Industry-Class Root of Trust IP

3DIC Physical Verification, Siemens EDA and TSMC

February 7, 2023April 10, 2023

3DIC Physical Verification, Siemens EDA and TSMC

3DIC Physical Verification, Siemens EDA and TSMC
by Daniel Payne on 02-07-2023 at 10:00 am
Categories: EDA, Foundries, Siemens EDA, TSMC

At SemiWiki we’ve written four times now about how TSMC is standardizing on a 3DIC physical flow with their approach called 3Dblox, so I watched a presentation from John Ferguson of Siemens EDA to see how their tool flow supports this with the Calibre tools. With a chiplet-based packaging flow there are new physical verification challenges, so the response at Siemens EDA was to develop Calibre 3DSTACK, which supports 3DIC and enables thermal analysis.

2.5DIC Interconnect

Physical checks for DRC ensure that substrate interfaces are correct with: alignment, overlaps, scaling and die-to-die spacings. LVS checking determines if connectivity through the interposer or package RDL are correct, compared to the golden netlist. Even the parasitics formed through the packaging interconnect need to be extracted and analyzed, as it impacts signal integrity and timing margins.

3D DRC and LVS

An early approach at 3DIC for LVS verification was to run it separately for each die to die interface, but that is impractical, instead the approach used with Calibre 3DSTACK is to check the full assembly, both DRC and LVS, with one deck, using one run.

To actually design and plan your 3DIC package assembly there’s another Siemens EDA tool called Xpedition Substrate Integrator (XSI), and that allows you to create the heterogeneous rule file, plus generate the source netlist. 3DIC package design and verification tools are shown below:

XSI and Calibre 3DSTACK

TSMC supplies the Assembly Design Kits (ADK) to support their 3Dblox tool flow, where it’s like a LEF/DEF flow, but in 3 dimensions now.

3Dblox package

Physical verification checking using the 3Dblox format is automated in this tool flow with Calibre 3DSTACK, and is independent of which tool creates the 3Dblox data.

3Dblox to Calibre 3DSTACK tool flow

In addition to 3DIC physical verification, there are new reliability issues like thermal, as the chiplets are placed in closer proximity. Temperature increases slow down silicon switching times and shorten semiconductor lifespan, which could lead to a timing or reliability failure. To find out how the package assembly impacts each chiplet, there’s another Siemens EDA tool, Simcenter Flotherm, to support the development of a thermal digital twin. With this you can get fast analysis, while in the early planning steps. Analysis results as static or dynamic heat maps are shown at the assembly, die or IP level. You can even get a post-layout netlist with the temperature coefficients of each device, which is used for signal integrity and timing analysis.

Simcenter Flotherm flow

Starting from a 3Dblox file, this thermal flow uses a 3DSTACK syntax, creating individual chip power maps across the assembly. Engineers will see wave forms or animated heat maps of the temperatures, or power can be shown at the chip or assembly level. Constraints can be specified, and then during thermal simulation any warnings or failures are noted.

Calibre and 3Dblox thermal flow

Adding thermal capabilities to support 3DIC packaging at Siemens EDA required close collaboration with TSMC.

Summary

The market excitement of 3DIC design also brings about new technology challenges, like how to perform physical verification with DRC and LVS in the most efficient method. TSMC has standardized in one format, the physical stacking and logic connectivity information, calling it 3Dblox. Siemens EDA with Calibre 3DSTACK fully supports the 3Dblox format in their DRC and LVS flows. Designing and planning 3D package assemblies is done with XSI, and new thermal analysis also uses the 3Dblox format. Thermal analysis for 3DIC packaging is also possible, allowing products to be designed to meet reliability goals.

The EDA, foundry and IP communities have collaborated together to face the new 3DIC design and verification challenges, allowing our economy to enjoy a steady stream of new products that are now reaching 100 billion transistors. The future of 3DIC is bright indeed.

Related Blogs

February 7, 2023April 10, 2023

Advances in Physical Verification and Thermal Modeling of 3DICs

Advances in Physical Verification and Thermal Modeling of 3DICs
by Peter Bennet on 02-07-2023 at 6:00 am
Categories: EDA, Foundries, Siemens EDA, TSMC

If, like me, you’ve been paying too little attention to historically less glamorous areas of chip design like packaging, you’ll wake up one day and realize just how much things have changed and continue to advance and how interesting it’s become.

One of the main drivers here is the increasing use of chiplets to counter the decreasing – indeed vanishing – cost gains from the latest process shrinks by allowing finer grain mapping of large sub-system blocks to their optimal process technology and optimise block reuse and design resources.

This is the sort of package scenario we’re dealing with (let’s call this an assembly of components).

The expanding world of 2.5D and 3D packaging falls between monolithic chip and PCB design, so both EDA and system level tools must be brought together to automate the process. Tasks like properly automating intra-package connectivity, checking vertical plane connections and more precise thermal modeling.

As with almost everything else in EDA these days, that means ever closer cooperation between EDA tool vendors, manufacturing and designers.

Siemens and TSMC’s work on 3DIC to jointly develop the TSMC 3Dblox standard unified design ecosystem based around Siemens’ Calibre 3DSTACK and c tools is a good example. John Ferguson’s presentation at TSMC OIP last October covered the advances here in both logical and physical verification and thermal analysis. Let’s take a closer look.

Closing the gaps in 3D Physical Verification

There are some obvious challenges here with 3DIC structures.

Processes may share layer names, whilst having different characteristics
Pin and pad names on components may be equivalent, but use different names
Tools need to create a combined PV deck, netlist and physical DB to verify the entire assembly and still maintain the correct rules for individual components
Potentially different input file formats for the components.

Packaging with heterogeneous process die creates new challenges for physical verification (PV), mainly in preparing a complete and accurate DB. Calibre 3DSTACK (see diagram below) already handled much of this PV prep – tasks like compiling the assembly physical DB with a single PV deck and computing the correct coupling between stacked die.

Adding Siemens’ Xpedition Substrate Integrator (XSI) planning tool closes the remaining gaps of describing the required components and connectivity (analagous to a spec or custom schematic), creating a merged netlist and managing the design DB; even automating the Calibre 3DSTACK verification.

One thing remains – finding a way to create adequate “library models” and “design rules” for the components. TSMC’s new 3DBlox approach does this with Assembly Design Kits (APDK) to describe the connectivity, process and assembly characteristics and design rules for each component.

Putting this all together we get a flow where can we prepare, run and debug the full assembly PV.

Thermal Analysis

3D packaging also creates greater thermal challenges including:

greater interaction between die
tougher heat dissipation challenge – greater power density due to 3D stacking
modeling vertical thermal gradients becomes necessary
modeling heatsink interaction for 3D die

Transistor performance strongly depends on temperature, so such thermal effects cannot be ignored. And these aren’t just signoff checks – we need good thermal and power modeling very early in the design and integrated into the ASIC design flow, since late changes here will create major rework.

With physical verification, the challenge was more one of verifying the top-level and component interfaces. Here it’s more about understanding the impact of the overall system on the components – and then how that feeds back into the top-level system.

A further collaboration with TSMC extended a flow built around the existing Siemens Calibre 3DSTACK and SimCenter Flotherm tools, reusing much of the infrastructure from the PV flow.

Analysis, including static and dynamic heat maps, can be carried out at assembly, die or IP level and power analysis run using mPower. Device temperature coefficients can be extracted for more precise signal and timing analysis.

Summary

Siemens and TSMC have put together a design methodology and flow to support current and future 3DICs based on proven tools (Calibre 3DSTACK and SimCenter Flotherm and with particular attention on simplifying configuration and modeling (3DBlox) and early design use. It’s something that should continue to scale as increasingly sophisticated 3D packaging technology arrives.

It’s also noteworthy that Siemens won a TSMC OIP Partner of the Year award for this work.

Further Information

The TSMC OIP presentation (“TSMC 3Dblox™ simplifies Calibre verification and analysis”) is available until May for readers with the original event registration link and code provided by TSMC.

Find out more about Calibre physical verification and 3DSTACK here:

https://eda.sw.siemens.com/en-US/ic/calibre-design/physical-verification/

https://eda.sw.siemens.com/en-US/ic/calibre-design/physical-verification/3DSTACK/

A white paper “Taking 2.5D/3DIC physical verification to the next level” is also available.

For Siemens Flotherm thermal analysis check here:

https://www.plm.automation.siemens.com/global/en/products/simcenter/flotherm.html

Also Read:

Achieving Faster Design Verification Closure

Siemens Aspires to AI in PCB Design

Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward

February 6, 2023February 7, 2023

Privacy? What Privacy?

Privacy? What Privacy?
by Roger C. Lanctot on 02-06-2023 at 10:00 am
Categories: Automotive, Security

It seems as if every day brings news of yet another company that is using artificial intelligence to leverage smartphone data for “non-invasive” analytics of human movement. Our smartphones and smartwatches and fitbits can detect whatever activity we are doing, how well or poorly we are doing it, how it is affecting our mood, and whether we are drowsy, drunk, or suffering some undiagnosed infirmity.

Television commercials from Apple and Google tout the benefits of this non-invasive invasion of privacy – not unlike the privacy annihilation of Google Search. It reminds me of Fullpower founder (and reputed smartphone inventor) Philippe Kahn’s description of a human being’s movements being the equivalent of a signature or fingerprint. Kahn has leveraged biosensing analytics associated with smartbeds to diagnose ailments and predict menstrual cycles.

The implications of this work can as easily apply to automobiles. At the Drive TLV startup event on the Georgia Tech campus in Atlanta this week, a ConActions executive described how the company leverages steering wheel data to assess a driver’s cognitive state – fatigue, inattention, anxiety, or inebriation.

ConActions’ work is being subject to validation and testing by Volkswagen and Hyundai, among others. The implications are considerable. If the mere act of steering a car can reveal such a wide range of conditions, what further conclusions can be drawn from a deeper dive into the full suite of sensors in a typical vehicle.

Of course, regulators are increasingly requiring driver monitoring systems – literally driver-facing cameras – and passenger detection systems including infra-red and radar sensors inside vehicles. We all let our guards down for Google to peer into some of our deepest (darkest?) thoughts yet no one stops to consider what a privacy defeating operating environment the average car represents.

This is one of many reasons why vehicle data protection and consent management are so essential for the future of connected cars. Vehicle data companies such as Aiden, for one, have gone out of their way to introduce in-vehicle consent agreements before sharing data.

One industry that is drooling at the prospect of turning small bits of vehicle data into huge chunks of corporate value are insurance companies. Just as smartphone makers are happy to tout their analytical chops, insurance company experts are pressing hard to integrate smartphones and car connections into the insurance underwriting process.

More than 10 years after Progressive Insurance introduced its Pay As You Drive program around vehicle tracking technology, the insurance industry continues to press the car connectivity button with a combination of smartphone apps (to track driving as well as to file claims) and so-called OBD-II plug-in devices and other aftermarket add-ons. Insurance industry visionaries routinely highlight the merits of connected car data for enhancing insurance underwriting and fundamentally rewiring the industry.

The enthusiasm for connected car-based insurance is driven by the reality that insurers are typically forced to rely on historical driving records and credit reports to build their current underwriting models – especially after regulators have denied their ability to use location or gender metrics that might impact protected classes of consumers. Devices such as Progressive’s Snapshot that focus on the amount of driving, time of day, and harsh braking or acceleration have been found to be effective tools to lower the cost of customer acquisition and extend the period of customer retention and lifetime customer value – i.e. reduce customer churn.

All of the reasons that make connected car-insurance so attractive to the underwriters are precisely the things that ought to give customers anxiety and agita. Does anyone really trust an insurance company to properly handle and protect customer data? Really? Count me out.

This is why I find the value proposition posed by local Atlanta startup Mile Auto so attractive. I visited with founder Fred Blumer while I was in town for the Drive TLV event.

Just a few years old, but already being offered directly to consumers by OEMs such as Porsche, Honda, and Hyundai, Mile Auto is a mileage-focused car insurance product perfectly suited to low mileage drivers. The application requires “no hardware and no app,” according to its founder, and currently has 30 full-time employees.

Mile Auto is neither the first nor the only auto insurance startup to attempt to leverage mileage-focused underwriting. MetroMile was pursuing this path prior to its acquisition by Lemonade last year. Root is another. Both Root and MetroMile consider driver behavior as well. Both companies struggled to build value with MetroMile launching a SPAC at a billion-dollar valuation that ultimately spiraled downward. Root took the IPO route, with a similar poor outcome.

Mile Auto bases its underwriting on the user literally taking a picture of their car’s odometer every month. It doesn’t get much simpler and less invasive than that. The result has been – with limited advertising or promotion – 15,000 insured customer vehicles across 11 states with exceptionally low customer acquisition costs and superior lifetime value metrics.

I personally never understood the appeal of connected car insurance – especially after my experience with State Farm Drive Safe and Save many years ago. While State Farm insisted on its customer portal that it was saving me money, it was painfully clear to me at the time that it was not. Today, my wife and I and our three sons are all on Geico – and no one is being digitally monitored by their insurance company.

Mile Auto can’t save you from the privacy violation zone represented by your smartphone, your car, or your search, but it can keep your insurance company at bay. I think it’s a great idea – if you are a low mileage driver. Post-COVID, aren’t we ALL low mileage drivers?

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ATSC 3.0: Sleeper Hit of CES 2023

ZoneCast Blast Misses Its Mark

To EV or NOT to EV?

February 6, 2023March 26, 2023

KLAC- Weak Guide-2023 will “drift down”-Not just memory weak, China & logic too

KLAC- Weak Guide-2023 will “drift down”-Not just memory weak, China & logic too
by Robert Maire on 02-06-2023 at 6:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services

-Business will “drift down” over the course of 2023
-Not just memory is weak- China issue, foundry/logic slowing
-March guide worse than expected (Like Lam)
-Backlog likely saw push outs & cancelations but still long

Good quarter but weak guide

Much as we saw with Lam, KLA reported a beat on the December quarter but a weaker than expected guide on the March quarter as the industry is falling faster than most believe. Revenue came in at $3B with EPS of $7.38 versus street of$2.82 and EPS of $7.10. Guidance was for revenues of $2.35B +-$150M and EPS of $5.22+-$0.70 versus street of $2.55B and $5.89, similar to the miss in guide that Lam also reported

2023 will be H1 weighted

Management said that business would likely drift down through the year. Sounds like projects may have been pushed out and backlog will get reduced as we go through the year .
It obviously takes some time for the high rate of spend to slow.

Backlog still high but will drop

Management said that 45-50% of backlog was over 12 months in length. How stable the backlog is may be open to question as we will see pushes and pulls with more pushes than pulls as schedules get adjusted. While KLA’s backlog is second only to ASML they are more vulnerable to push outs and delays or cancellations of quicker turn products.

Its not just memory issues but China and foundry/logic as well

China business looks to be close to cut in half from levels prior to the embargo. While Lam may be the poster child for weak memory, KLA may be more impacted by the China embargo. The weak quarter out of Intel reminds us that foundry/logic is also weak though perhaps not down as sharply as memory or China. This “triple whammy” of memory, China & foundry/logic is obviously impacting all semi equipment makers with different segments impacting each participant differently

Length and depth of down cycle a great unknown

Management did not want to comment on the length or depth of the downturn other than to say that KLA should do better than most of their peers (with the obvious exception of ASML)

As we have said a while ago, we think 2023 is looking a lot like a write off with no real recovery until 2024 at the earliest. While KLA tends to have strong backlog, it could run out if the downturn lasts too long and then results will be a bit less predictable.

Welcome to reality

We think many investors do not believe the industry is in as bad a downturn as actually exists. Many ignored the dire guidance from Lam coupled with the very serious actions taken by the company to reduce costs which obviously wouldn’t have been taken unless there was a concern of a prolonged downturn.

While we didn’t hear specifically about layoffs from KLA, we are sure that they are selectively cutting expenses as they said they would “stabilize” spending which means reduce. This sounds like although things are not great, they are not as bad as they are at Lam

The stocks

With KLAC adding to Lam’s view that 2023 will not only be down but will be H1 weighted with continuing increasing weakness through the year, we are hardly motivated to buy any equipment stock akin to catching a falling knife.
We may see some false rallies as people may think the worst is over or Q1 is the bottom or other falsely optimistic views but we are in the midst of a good, old fashioned down cycle of the sort we haven’t seen in quite a while and some lesser experienced investors and analysts have never seen.

The long term secular trends remain as positive as ever but when they will return is anyone’s guess. In the mean time we could see this bouncing drift down the bottom of the cycle. Because this down cycle is not caused by a singular event, it is likely that we will need at least two of the three factors to improve before we see things move upward again.

KLA remains a nice house in a declining neighborhood but that doesn’t make us feel comfortable.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

Hynix historic loss confirms memory meltdown-getting worse – AMD a bright spot

Samsung- full capex speed ahead, damn the downturn- Has Micron in its crosshairs

Lam chops guidance, outlook, headcount- an ugly, long downturn- memory plunges

Podcast EP142: The Drive Toward a More Sustainable Semiconductor Industry with EMD Electronic’s Anand Nambiar

Podcast EP142: The Drive Toward a More Sustainable Semiconductor Industry with EMD Electronic’s Anand Nambiar
by Daniel Nenni on 02-03-2023 at 10:00 am

Dan is joined by Anand Nambiar, Executive Vice President and Global Head of Semiconductor Materials at EMD Electronics, the North American Electronics business of Merck KGaA, Darmstadt, Germany. Anand has over 23 years’ experience in the semiconductor industry. His previous roles include Associate Director – Quality at Nikon Inc., Vice President of Operations at Cascade Microtech, Operations Director at AZ Electronic materials, and Managing Director of the Optronics Division at AZ Electronic Materials up to its acquisition by EMD Electronics, He has headed the semiconductor materials business for the past four years, overseeing its high-profile acquisition of Versum Materials. Anand has also led EMD Electronics’ Biopharma and Consumer Health business in India.

Dan explores the far-reaching impact EMD Electronics is having on the semiconductor industry with Anand. Current programs and their impact on power and greenhouse gas emissions, as well as new initiatives are discussed, with an eye toward building a cleaner and more sustainable semiconductor industry.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

February 3, 2023March 26, 2023

Hynix historic loss confirms memory meltdown-getting worse – AMD a bright spot

Hynix historic loss confirms memory meltdown-getting worse – AMD a bright spot
by Robert Maire on 02-03-2023 at 8:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

-Hynix reports worst downturn in 10yrs – Already in red ink
-If the #2 memory maker is already negative what does it say?
-Confirms our view of 2023 write off- maybe 2024 better?
-Micron Mangled? & Toshiba Toast?- Buyers advantage

Hynix posts record $1.4B loss- worst in 10 years

Not all that surprisingly Hynix reported a loss making quarter. As the second largest memory chip maker after Samsung the drop was rather rapid.
The company also said the current memory situation is getting worse in the first quarter.

Hopes are for a 2024 recovery. Right now there is no firm evidence to point to other than the typical refrain from analysts in prior cycles saying that things will be better in 6 months (just wishful thinking at this point).
Hynix has obviously cut Capex and output.

Memory makers can slow but not stop output

Unlike OPEC and oil wells you just don’t hit the stop button at a fab. The vast majority of the cost of making any semiconductors is the depreciation of the equipment and bricks and mortar. The variable costs of consumables & labor is relatively small. This means that once a fab is built and complete you tend to run it at maximum capacity for the rest of its life as the marginal cost is low.

That marginal cost is also quite low as compared to the fully loaded cost so memory makers can get pushed to very low, loss making levels before they would ever consider stopping production. They can however, slow production by a small amount but all that means is that they will likely lose share to other memory makers who don’t slow.

Samsung can push pricing to the edge

All this suggests that dominant players, like Samsung, can push memory pricing down to the point that they can still tolerate (not happily) but below the level at which other competitors are profitable, thereby choking off the oxygen in the room. Obviously Hynix as the number two memory maker and Micron as a more distant 4th or 5th can get quickly pushed into the red.

This situation can persist for a long time if demand doesn’t recover.
As we have previously explained capacity can still increase without large capital expenditures due to technology advancement.

What is really needed to end the memory meltdown is for demand to increase…..the industry will never be able to cut production enough to get supply and demand back into balance….it will just not happen.

This suggests that the current memory issue is more of a macro economic demand recovery issue than an over supply issue….meaning that the resolution is not in the hands of the memory makers. The best they can do is take advantage of the situation which Samsung is doing.

A memory buyers market

It has been a memory sellers market for a very long time as makers have set pricing.

The tables have now turned

We have heard, from several different sources, that large buyers of memory are dictating terms and making deals at attractive pricing and terms. Memory makers desperate for buyers are willing to cut deals for large orders of memory at fixed terms to try to hold onto market share or gain share from others.

This implies that we may see some market share shifts created by the downturn as some makers will make deals and others not so.

AMD a minor bright spot in a dark industry

AMD posted better than expected results as they continue to do well and gain share. This stands in obvious contrast to Intel not that long ago. While this is good for AMD it is really just further proof of the importance of TSMC that produces the chips that are successful.

It says that TSMC continues to do a great job of execution as it completely dominates the industry.

This is not to say that AMD has nothing to do with its own success but just that TSMC remains “the man behind the curtain” for most successful tech companies such as AMD, Apple, Nvidia etc; etc;.

Micron, Toshiba & Hynix need further cuts

While memory makers be not be able to avoid red ink in the current memory meltdown they need to reduce the hemorrhaging as much as possible to extend the runway beyond the length of a long downturn.

This likely means more layoffs, more capex cuts, project cancelations.

It is also important for companies to have gas left in the tank for when the industry does finally recover so they can participate and not be left permanently wounded or dead. Even Yangtze memory in China has reported a 10% headcount reduction.

The stocks

Obviously Hynix is just more proof of what we already knew since June. The main difference is the underscoring of exactly how long and deep the memory downturn will be. We haven’t seen significant red ink in a very long time and in many cases longer ago than many investors actually can remember or have experience with so many may be in uncharted territory. We continue to warn investors that this will not be a “snap back” type of short lived downcycle as we have seen in brief respites of an otherwise bull tech market.

Companies that continue to ride above the fray include ASML and TSMC, although not cheap for a reason. We also warn investors that we have yet to know the bottom, at least in the memory market, and it is wrong to assume its in the next quarter or two.

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

Lam chops guidance, outlook, headcount- an ugly, long downturn- memory plunges

ASML – Powering through weakness – Almost untouchable – Lead times exceed downturn

Where there’s Smoke there’s Fire: UCTT ICHR LRCX AMAT KLAC Memory