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Chiplet Q&A with John Lee of Ansys

Chiplet Q&A with John Lee of Ansys
by Daniel Nenni on 05-19-2023 at 6:00 am

SNUG Panel

At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was John Lee, Head of Electronics, Semiconductors and Optics at Ansys.

How is the signoff flow evolving and what is being done to help mitigate the growing signoff complexity challenge?

With multi-die, there are three key challenges that I’ll highlight and then talk about how we can best address those. First, the lines between silicon systems are blurring so we now have what we call multi-scale problems, where you’re looking at nanoscale effects such as cell heat at a transistor level, but then you need to go to centimeters or potentially meters scale effects as you look at multiple dies in the package and the electronic system.

The second one, I think is obvious, it’s Multiphysics. As you’re packing in more and higher signal speeds we generate more thermals, and you start stacking thermal dies on top of each other, generating heat. There are going to be severe mechanical effects that you also need to account for.

The third is a Multi-organization challenge. Typically, as we look across the industry or a customer base, you have a chip team, you have a package team, and some of the dies’, may not even be coming from your own company so there’s an organizational challenge that needs to be addressed.

We call that the 3Ms: Multi-scale, Multi-physics, and Multi-organization. And really to support that from a signoff standpoint, we have to start with the physics, right? If we’re not accurately modeling electromagnetics, not accurately modeling the thermals; the power integrity, signal integrity, and thermal integrity are a non-starter.

Thus, we need to provide an open and extensible platform. A platform implies scaling out very nicely in terms of computing, for a truly transistor design. How do you scale up that compute efficiently, open and extensible, which gets to the third part, which is a partnership, and the scale and scope of the problems that we’re solving around multi-die. It really requires a village. For example, the Ansys platform, working closely with the Synopsis platform is a great example of an open extensible ecosystem that better solves the challenges that we’ve seen together.

How is the increased learning curve for these Multiphysics effects being addressed?

It’s been pretty steep, to your point, Ansys has been doing mechanical thermal CFD simulation for over 50 years so it’s not that we don’t know how to solve these differential equations. If you look at, and specifically another example around thermal, typically the semiconductor companies might have a thermal team. That thermal was never really owned by the chip team or the IP team or the package team. Or if they did, they each had a different view of that. And then, in partnership with the , probably over the last five years it’s really about how do we take thermal into the workflow that’s silicon validated, that also is computational efficient.

As I mentioned earlier, we’ve seen our customer roadmaps with 2.5D and 3D.

There’s going to be a trillion transistor design pretty soon. And then a trillion transistors could mean 10 trillion geometries. And then from a thermal standpoint, we’d like to then mesh that into a hundred trillion elements, which of course is computationally impossible. And so how do we take that into a workable flow that can also be signed off, but also work in conjunction with 3D IC compilers. So, we have early system-level awareness. We do a lot of co-innovation with companies like Synopsys and TSMC.

We’ve used AI/ML, to guide us in how we can identify hotspots and how we can better optimize meshing. This has forced us to look more heavily at using reduced-order models to do abstractions so we can do quicker system-level simulations. And I’d say with all the experience that Ansys has around solving these equations we certainly feel like we have market leadership, though I’d say that we’re still only halfway there. We probably have another five years of hard work ahead of us to take these systems to the power and usability that we want them to be. And AI is going to be part of that, right? AI is already part of it, thankfully.

What is the customer’s view of the reliability challenge?

Well, it certainly has increased, and ’ example is a perfect example where reliability has become a primary concern, but it also extends if you’re building out a 5G base station that’s not in an air-conditioned warehouse or if you’re scaling out a huge data center. There are various use cases where reliability has an increasing problem and we’ve invested in this area.

We have a product called functional safety ISO 20620 compliance and building out, going from spreadsheets to formal systems for tracking reliability, which is extremely important. We’ve also put some focus on the software side. We had originally been investing in automotive software systems and making sure that they are fail-safe, but we’ve seen a lot of adoption from that product line into the automotive industry. But for my team, the most relevant work has really been with foundries like TSMC and making sure that we use computational physics to better dial in reliability.

Also Read:

Ansys Acquires Another!

Multiphysics Analysis from Chip to System

Checklist to Ensure Silicon Interposers Don’t Kill Your Design

HFSS Leads the Way with Exponential Innovation


eFPGA Enabled Chiplets!

eFPGA Enabled Chiplets!
by Daniel Nenni on 05-18-2023 at 10:00 am

Achronix eFPGA IP

With our continuing chiplet coverage I found this of great interest. I have always felt that eFPGAs and chiplets are a natural fit for the next generation of chip design and this is an excellent example. As we design with chiplets one of the challenges is verification/validation in regards to performance and interoperability. This partnership between Achronix Semiconductor and applied research institute Fraunhofer is a great example of how to address these challenges.

We have been working with Achronix Semiconductor since 2017 and know them well. Achronix stands out as they are the only independent high-end FPGA provider now that Altera and Xilinx have been acquired. This allows them to be much more customer centric. Achronix is also the only big FPGA company that provides eFPGA IP technology.

Fraunhofer is an interesting organization. I see them at conferences but have never worked with them directly. Fraunhofer-Gesellschaft, founded in 1949, is based in Germany and is the world’s leading applied research organization. Fraunhofer-Gesellschaft currently operates 76 institutes and research units throughout Germany. Over 30,000 employees, predominantly scientists and engineers, work with an annual research budget of €2.9 billion.

Here is the original announcement released last month with the associated links for more information. Definitely worth a read:

Fraunhofer IIS/EAS Selects Achronix Embedded FPGAs (eFPGAs) to Build Heterogeneous Chiplet Demonstrator 

Collaboration to create an eFPGA-enabled chiplet solution aimed at validating next-generation chip-to-chip interconnect technology.

Santa Clara, Calif., and Dresden, Germany, April 25, 2023 – In a continuing commitment to enabling industry-leading solutions for the semiconductor market, Fraunhofer IIS/EAS, leading-edge applied research institute in the field of advanced package solution design, and Achronix Semiconductor Corporation, the industry’s only independent supplier of high-end FPGAs and eFPGA IP solutions, are entering today in a partnership to build a heterogeneous chiplet solution to validate performance and interoperability in advanced high-performance system solutions.

The Fraunhofer institute provides system concepts, design services and fast prototyping in most advanced packaging technologies and will make use of Speedcore™ eFPGA IP from Achronix in its next project. The multi-chip system solution will be composed of several chiplets that will be used to explore chip-to-chip transaction layer interconnects such as Bunch of Wires (BoW) and Universal Chiplet Interconnect Express (UCIe).

Chiplets are rapidly being adopted for high-performance, heterogeneous multi-chip solutions and enable lower latency, higher bandwidth and lower cost than discrete devices connected via traditional interconnects on a printed circuit board. One key application that will be covered in this project is the connection of high-speed ADCs together with Achronix® eFPGA IP for preprocessing in radars as well as wireless and optical communication. Achronix Speedcore eFPGA IP is playing an important role in this application with low latency and reconfigurability while delivering high-performance data acceleration required in many applications.

The result of this project will create a demonstration platform suitable for applications such as 5G/6G wireless infrastructure, ADAS and high-performance test and measurement equipment. The findings of this cooperation will be communicated in a later press release and will be of interest to all semiconductor market actors seeking interface compatibility with their semiconductor chiplets.

About Fraunhofer IIS/EAS

The Fraunhofer Institute for Integrated Circuits IIS is a world leader in research on microelectronic and IT system solutions and services. Scientists at the institute’s EAS division in Dresden are working on key technologies for cutting-edge electronics systems. Among other things, the researchers focus on new design concepts to meet the challenge of the constant miniaturization of semiconductor components and the growing complexity of integrated circuits. The goal is to ensure the swift, resource-efficient, error-free, safe and secure development of electronic systems. Another focus is on new “More than Moore” technologies, which make it possible to combine a wide variety of assemblies in a single component.

About Achronix Semiconductor Corporation

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-end FPGA-based data acceleration solutions, designed to address high-performance, compute-intensive and real-time processing applications. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and licensed eFPGA IP solutions. Achronix Speedster®7t FPGA and Speedcore™ eFPGA IP offerings are further enhanced by ready-to-use VectorPath™ accelerator cards targeting AI, machine learning, networking and data center applications. All Achronix products are fully supported by the Achronix Tool Suite which enables customers to quickly develop their own custom applications.

Achronix has a global footprint, with sales and design teams across the U.S., Europe and Asia. For more information, please visit www.achronix.com.

Follow Achronix

Website: www.achronix.com
The Achronix Blog: /blogs/
Twitter: https://twitter.com/Achronixcorp
LinkedIn: https://www.linkedin.com/company/57668/
YouTube: https://www.youtube.com/user/AchronixCorp

Contacts

Sandra Kundel
Press Relations
Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS
Muenchner Strasse 16, 01187 Dresden, Germany
Phone +49 351 45691-152
pr@eas.iis.fraunhofer.de

Bob Siller
Achronix Semiconductor Corporation
408-889-4142
bobsiller@achronix.com

Also Read:

The Rise of the Chiplet

Achronix on Platform Selection for AI at the Edge

WEBINAR: FPGAs for Real-Time Machine Learning Inference


Opinions on Generative AI at CadenceLIVE

Opinions on Generative AI at CadenceLIVE
by Bernard Murphy on 05-18-2023 at 6:00 am

Generative AI

According to some AI dreamers, we’re almost there. We’ll no longer need hardware or software design experts—just someone to input basic requirements from which fully realized system technologies will drop out the other end. Expert opinions in the industry are enthusiastic but less hyperbolic. Bob O’Donnell, president, founder and chief analyst at TECHnalysis Research moderated a panel on this topic at CadenceLIVE with panelists Rob Christy (Technical Director and Distinguished Engineer, Implementation – Central Engineering Systems at Arm), Prabal Dutta (Associate Professor, Electrical Engineering and Computer Sciences, at University of California, Berkeley), Dr. Paul Cunningham (Senior Vice President and General Manager of the System & Verification Group at Cadence), Chris Rowen (VP of Engineering, Collaboration AI at Cisco) and Igor Markov (Research Scientist at Meta)—people who know more than most of us about chip design and AI. All panelists offered valuable insights. I have summarized the discussion here.

Will generative AI change chip design?

The consensus was yes and no. AI can automate much of the human-in-the-loop interaction on top of necessary building block technologies: Place-and-route, logic simulation, circuit simulation, etc. This allows us to explore a broader—perhaps much broader—range of options than would be possible through manual exploration.

AI is fundamentally probabilistic, ideal where probabilistic answers are appropriate (generally improving on a baseline) but not where high precision is mandatory (e.g. synthesizing gates). Further, generative models today are very good in a limited set of fields, not necessarily elsewhere. For example, they are very inefficient in math applications. It is also important to remember that they really don’t learn skills—they learn to mimic. There is no underlying understanding of electrical engineering, physics, or math for example. In practical use, some limitations might be offset with strong verification.

That said, what they can do in language applications is remarkable. In other massive domain-specific datasets, such as in networking, large models could learn structure and infer many interesting things that have nothing to do with language. You could imagine superlinear learning in some domains if learning could run against worldwide corpora, assuming we can master thorny IP and privacy issues.

Can generative methods boost skill development?

In semiconductor and systems design, we face a serious talent shortage. Panelists believe AI will help younger, less experienced engineers accelerate quicker to a more experienced performance level. Experts will get better too, getting more time to study and apply new techniques from constantly expanding frontiers in microarchitectural and implementation research. This should be a reminder that learning-based methods will help with “every experienced designer knows” knowledge but will always be behind the expert curve.

Will such tools allow us to create different types of chips? In the near term, AI will help make better chips rather than new types of chips. Generative models are good with sequences of steps; if you are going through the same design process many times, AI can optimize/automate those sequences better than we can. Further out, generative methods may help us build new kinds of AI chips, which could be interesting because we are realizing that more and more problems can be recast as AI problems.

Another interesting area is in multi-die design. This is a new area even for design experts. Today, we think of chiplet blocks with interfaces built up as pre-determined Lego pieces. Generative AI may suggest new ways to unlock better optimizations, providing different answers than even the experts might quickly find.

Pitfalls

What are the potential pitfalls of applying generative AI to chip and or system design? We ourselves represent one problem. If the AI is doing a good job, do you start to trust it more than you should? Similar questions are already a concern for autonomous driving and autonomous weaponized drones. Trust is a delicate balance. We can trust but verify, but then what if verification also becomes learning-based to deal with complexity? When verification AI is proving the correctness of AI-generated design, where do we cross a line between justified and unjustified trust?

ChatGPT is a cautionary example. The great fascination and the great fallacy of ChatGPT is that you can ask it anything. We’re amazed by the specific smartness and by the fact that it covers so many different areas. It feels like the automatic general intelligence problem has been solved.

But almost all real-world applications will be much narrower, judged on different criteria than an ability to amaze or entertain. In business, engineering and other real-world applications we will expect high quality of results. There’s no doubt that such applications will progressively improve, but if hype gets too far ahead of reality, expectations will be dashed, and trust in further advances will stall.

More pragmatically, can we integrate established point skills into generative systems? Again, yes and no. There are some augmented models that are very productive and able to handle arithmetic and formula manipulation, for example, WolframAlpha which is already integrated with ChatGPT. WolframAlpha provides symbolic and numerical reasoning, complementing AI. Think of AI as the human-machine interface and the WolframAlpha augmentation as the deep understanding behind that interface.

Is it possible to bypass augmentation, to learn and load skills directly into the AI as modules as Neo was able to learn King Fu in the Matrix? How local is the representation of such skills in language models? Unfortunately, even now, learned skills are represented by weights in the model and are global. To this extent, loading a trained module as an extension to an existing trained platform isn’t possible.

There is a somewhat related question around the value of worldwide training versus in-house-only training. The theory is that if ChatGPT can do such a good job by training on a global dataset, then design tools should be able to do the same. This theory stumbles in two ways. First, the design data needed for training is highly proprietary, never to be shared under any circumstances. Global training also seems unnecessary; EDA companies can provide a decent starting point based on design examples routinely used to refine non-AI tools. Customers building on that base, training using their own data, report meaningful improvement for their purposes.

Second, it is unclear that shared learning across many dissimilar design domains would even be beneficial. Each company wants to optimize for its own special advantages, not through a multi-purpose soup of “best practices”.

Hope for reuse in AI and looking forward

Given earlier answers, are we stuck with unique models for each narrow domain? It’s not clear that one architecture can do everything, but open interfaces will encourage an ecosystem of capabilities, maybe like a protocol stack. Apps will diverge, but there can still be a lot of shared infrastructure. Also, if we think of applications which require a sequence of trained models, some of those models may be less proprietary than others.

Looking forward, generative AI is a fast-moving train. New ideas are appearing monthly, even daily, so what is not possible today may become possible or solved in a different way relatively soon. There are still big issues of privacy in any area depending on training across wide datasets. Proving that learned behavior in such cases will not violate patents or trade secrets seems like a very hard problem, probably best avoided by limiting such training to non-sensitive capabilities.

Despite all the caveats, this is an area to be fearless. Generative AI will be transformative. We must train ourselves to better leverage AI in our daily lives. And in turn, applying our learning to be more ambitious for our use in design technologies.

Great talk. Hopeful, with good insights into limitations and practical applications.

Also Read:

Takeaways from CadenceLIVE 2023

Anirudh Keynote at Cadence Live

Petri Nets Validating DRAM Protocols. Innovation in Verification


Steep Decline in 1Q 2023

Steep Decline in 1Q 2023
by Bill Jewell on 05-17-2023 at 2:00 pm

Top Semiconductor Company Revenue 2023

The global semiconductor market dropped 8.7% in 1st quarter 2023 versus 4th quarter 2022, according to WSTS. This was the steepest quarter-to-quarter decline since a 14.7% drop in 1Q 2019. 1Q 2023 was down 21.3% from a year earlier, the largest year-to-year decline in thirteen years since a 30.4% drop in 1Q 2009. Revenues of the top fifteen semiconductor companies reflect this weakness, with a weighted average revenue decline of 12% in 1Q 2023 from 4Q 2022.

The hardest hit were the memory companies (Samsung, SK Hynix, and Micron Technology) which collectively dropped 26%. The sharpest falloffs of the non-memory companies were Intel (down 17%) and MediaTek (down 12%). Collectively, the 12 non-memory companies declined 7%. Four companies managed revenue gains in 1Q23 versus 4Q22. Nvidia has not reported its equivalent 1Q23 revenues, but its guidance from the prior quarter was a 7.4% gain. Qualcomm, Infineon, and Analog Devices also grew their revenues.

Comparing 1Q 2023 revenue rankings versus 4Q 2022, Intel is again number one after Samsung’s revenues dropped 32% in 1Q23. Broadcom and Qualcomm remain numbers 3 and 4, respectively. SK Hynix dropped from number 5 in 4Q22 to number 10 in 1Q23 with a 34% revenue decline. Nvidia and AMD each moved up a spot to 5 and 6. Infineon Technologies became number 7, passing Texas Instruments (TI) and STMicroelectronics which remain 8 and 9. Micron Technology remains number 11. Analog Devices rose two spots to number 12, with MediaTek and NXP Semiconductors slipping from 12 and 13 to 13 and 14. Kioxia dropped out of the top 15 with a 26% percent decline. Renesas Electronics entered the rankings at number 15.

We at Semiconductor Intelligence define semiconductor suppliers using the WSTS methodology. Only final sellers of semiconductors are included. Thus, foundries such as TSMC are not included since they generally sell their output to other semiconductor companies which are the final seller. This avoids double counting revenues. Also, companies which use semiconductors only in their own products, such as Apple, are not included.

The guidance for 2Q 2023 revenues versus 1Q 2023 is mixed. Of the 11 companies providing guidance, five expect increases and six expect decreases. The largest expected gains are 2.5% from NXP and 2.4% from Intel. Qualcomm has the largest expected decline at 9.3%. Weak end demand and continuing inventory adjustments in the channel are cited by many companies as factors in the cautious outlook. Automotive and industrial remain the bright spots, with five companies citing these sectors as growing or at least flat versus the prior quarter. The uncertainty of 2Q 2023 is reflected by the range of revenue guidance. The weighted average guidance for 2Q23 is a 1% decline from 1Q23. However, the weighted average high-end guidance is a 3% increase while the weighted average low-end guidance is a 5% decline, an 8 percentage-point difference.

As reported in the Semiconductor Intelligence April newsletter, shipments of the key end equipment were down sharply in 1Q 2023. IDC estimated PC shipments were down 29% from a year ago. Recent IDC estimates of 1Q 2023 smartphone shipments show a 14.6% drop from a year ago. Continuing inventory adjustments throughout the channel indicate semiconductor shipments will lag end equipment shipments. Once inventories return to target levels, they are likely to remain lean as end equipment makers will be reluctant to build inventories with the uncertain economic outlook.

Forecasts for the 2023 semiconductor market released within the last month range from a 20% drop from Future Horizons to an 11.2% drop from Gartner. Our latest forecast from Semiconductor Intelligence calls for a 15% decline. Given the weakness in 1Q 2023 and the cautious outlook for 2Q 2023, a double-digit fall-off for year 2023 is almost certain.

The growth rate of the semiconductor market in 2024 depends on the timing of the market recovery in 2023. Gartner’s May projection was an 18.5% gain in 2024, assuming a 70% increase in the memory market. We at Semiconductor Intelligence are more cautious. Our baseline forecast for 2024 is 9% growth. Our 2024 forecast range is from 3% to 15%.

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com

Also Read:

Steep decline in 1Q 2003

Electronics Production in Decline

Automotive Lone Bright Spot

Bleak Year for Semiconductors


Podcast EP162: How Lightelligence Changes the Compute Paradigm with Light

Podcast EP162: How Lightelligence Changes the Compute Paradigm with Light
by Daniel Nenni on 05-17-2023 at 10:00 am

Dan is joined by Hal Conklin, Vice President of Business Development for Lightelligence. Hal is an experienced strategic leader in the technology industry. Prior to joining Lightelligence, he spent 10 years at Arm and he also worked in executive management roles at several start-ups.

Hal provides details of a new and ground-breaking way to use light to address computing challenges as well as communication challenges. He outlines the substantial performance gains and power reduction that are possible with this new approach and details where it can be applied. You can learn more about the company at  www.lightelligence.ai.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


SPIE 2023 – imec Preparing for High-NA EUV

SPIE 2023 – imec Preparing for High-NA EUV
by Scotten Jones on 05-17-2023 at 6:00 am

Figure 1 Pellicle Transmission

The SPIE Advanced Lithography Conference was held in February. I recently had the opportunity to interview Steven Scheer, vice president of advanced patterning process and materials at imec and review selected papers that imec presented.

I asked Steve what the overarching message was at SPIE this year, he said readiness for High NA is key. He identified three key ecosystem areas:

  1. Mask and Resolution Enhancement Technology (RET) infrastructure.
  2. Materials, photoresist and underlayers.
  3. Metrology

The exposure tools are also of course key, but that isn’t what Steve talks to. Authors note – I will be doing a write up on ASML’s SPIE presentations as well.

Masks

Steve went on to list out mask related issues:

  • Mask 3d effects, such as focus shift and contrast loss – High NA is a low angle exposure making 3D effects more of an issue.
  • Low defectivity mask blanks and masks with low variability in roughness and CD
  • Low-n masks are needed to enable higher contrast and reduce mask 3D effects.
  • Optical Proximity Correction techniques.
  • Mask writing, multibeam.
  • Mask stitching – the smaller size of the scanner field requires that die be stitched together.
  • 4x one direction, 8x other direction requires a new type of mask design to enable stitching.
  • Pellicles for higher source energy.

In “CNT pellicles: Recent optimization and exposure results,” Joost Bekaert et.al., explored Carbon Nanotube pellicles (CNT).

ASML has 600-watt source systems on their roadmap, current pellicles based on metal silicide are only viable up to approximately 400 watts. Pellicles need to block particles, have high transmission, sufficient mechanical strength to be suspended over an approximately 110mm by 140mm area, and be durable. CNT has showed up to 98% transmission. EUV radiation is so energetic that it creates a hydrogen plasma that etches the pellicle eventually leading to pellicle loss of mechanical integrity. imec has been evaluating etch rates and how to stabilize the pellicle.

Etch rates can be evaluated by looking at transmission, as the Pellicle is thinned by etching, transmission increases. Figure 1 illustrates the transmission over time of a Pellicle subject to various conditions.

Figure 1. Pellicle transmission versus exposure time.

ASML evaluates pellicle transmission versus exposure time utilizing an offline plasma exposure tool and in this work, imec demonstrated CNT pellicle exposure up to 3,000 wafers (96 dies at 30 mJ/cm² per wafer), and showed correlation between the results obtained from actual scanner exposure and those from the offline tool.

Pellicles initially have volatile organic impurities from the manufacturing process that absorb EUV energy until they burn off, see the green and purple curves. Baking the Pellicle at high temperatures “purifies” the pellicle by burning off the contaminants resulting in etch rate dominated transmission changes. The slope of the two blue curves is due to the etch rate. The green curve illustrates a “coated” pellicle that exhibits a lower etch rate, however the coating reduces transmission and may not be compatible with very high-power levels.

Photoresist

Steve, then discussed photoresist.

For photoresist a 24nm to 20nm pitch is a sweet spot for High NA insertion with 16nm pitch the ultimate resolution. Chemically Amplified Resist (CAR) has poor performance below 24nm. Metal Oxide Resists (MOR) look promising down to 17nm or even 16nm. Defectivity is still an issue. Doses at for a 24nm pitch is 67mJ/cm2 for MOR and 77mJ/cm2 for CAR. MOR has some stability issues and the lower the dose the more reactive/less stable the resist is. These are challenges, not showstoppers.

In “Scaled down deposited underlayers for EUV lithography,” Gupta et.al., explored photoresist underlayers. As pitch is shrunk, for the same photoresist layer the aspect ratio increases and can lead to pattern collapse. Improved underlayer adhesion can address this. Alternately a thinner photoresist can be utilized to manage aspect ratio but this can lead to etch issues unless a high etch selectivity under layer can be found.

imec found that surface energy of deposited underlayers can be matched to the photoresist to achieve improved adhesions. Density tuning of the deposited underlayer can be utilized to provide improved etch selectivity.

In “Dry Resist Patterning Readiness Towards High NA EUV Lithography,” Hyo Sean Suh et.al., from imec and Lam explored Lam’s dry photoresist process. For N2+ and A14 processes Metal 2 pitch (M2P) is expected to be ~24nm with 15nm tip-to-tip (T2T) and then at A10 M2P will be ~22nm with <15nm T2T.

The Lam dry resist process is illustrated in figure 2.

Figure 2. Lam Dry Photoresist Process

Post Exposure Bake (PEB) was found to strongly drive dose reduction but affected bridges and roughness. Co-optimizing development and etch mitigates bridges and roughness and showed a robust process window for 24nm pitch L/S patterning.

In “Feasibility of logic metal scaling with 0.55NA EUV single patterning,” Dongbo Xu et.al. described an evaluation of what High-NA (0.55NA) system can achieve with single patterning.

They concluded that 24nm pitch looks achievable. 20nm looks promising in the horizontal direction but the vertical direction needs more work. 18nm pitch needs additional work.

EUV has proven to be a very challenging technology from a Line roughness and stochastic defect perspective. Directed Self Assembly (DSA) is a technology that has been around for a long time but hasn’t gotten much traction. DSA is now getting attention as a technique to address line roughness and stochastic defects for EUV.

In “EUV LITHOGRAPHY LINE SPACE PATTERN RECTIFICATION USING BLOCK COPOLYMER DIRECTED SELF ASSEMBLY: A roughness and defectivity study,” Julie Van Bel et.al. found that combining DSA with EUV is superior to DSA processes based on Immersion lithography with lower line width roughness and no dislocation defects.

In “Mitigating Stochastics in EUV Lithography by Directed Self-Assembly,” Lander Verstraete et.al. explored using DSA to mitigate stochastic defects in EUV processing.

The imec process to rectify line/space EUV defects is illustrated in figure 3.

Figure 3. EUV Line/Space Pattern Rectification by DSA.

The imec process to rectify defects in contact arrays is illustrated in figure 4.

Figure 4. EUV Contact Pattern Rectification by DSA.

EUV plus DSA looks very promising for line/spaces at a 28nm pitch with the primary defect being bridges. At a 24nm pitch improvement is needed with too many bridge defects. Defects correlate with the block copolymer formulation and anneal time.

For contact arrays EUV + DSA improves Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error and enables a lower dose.

Metrology

As film thicknesses are reduced metrology signal to noise ratios become a problem.

With EUV there is a defectivity process window, on one side there is a cliff where breaks in the pattern become an issue and on the other side of the windows there is a cliff where bridges between patterns become a problem.

When a new pitch is attempted there are a lot of defects that are driven down over time.

It is hard to measure a large enough area with sufficient sensitivity. E beam inspection is sensitive but slow, optical is fast but not sensitive. New 3D processes like CFET introduces additional challenges.

In “Dry Resist Metrology Readiness for High NA EUVL,” Gian Francesco Lorusso et.al, investigate Atomic Force Microscope (AFM), E Beam inspection and CD SEM for characterization of very thin photoresists.

Using the Lam dry photoresist process< CD SEM was shown to be viable down to 5nm thick photoresist.  As resist thickness decreased line roughness increased, printability of bridge defects decreased while break defects remained the same. Pattern collapse was only seen in thicker films. AFM measurements indicated film thickness decreases. E Beam showed good capture of defects even for very thing films.

In “Semiconductor metrology for the 3D era,” J. Bogdanowicz et.al., explore the challenges of metrology on 3D structures.

In the 3D era, the Z direction has become the new X/Y scaling. For logic devices, CFET and Semi damascene presents challenges, in memory 3D DRAM is a future challenge, and 3D interconnects for System Technology Co Optimization (STCO) are another challenge.

For Horizontal Nanosheet and CFET processes lateral recess and fill characterization and detecting residues and other defects in multilayer stacks will be critical. In 3D Memory high aspect ratio (HAR) hole/split profiling and similar to logic detecting buried defects and residues in multi layers films will be critical. For STCO applications integrity of bonding interfaces and alignment will be key.

For traditional surface metrology there is already a trade off between sensitivity and speed, now inspection depth versus lateral resolution is a key trade off. Figure 5 presents the probing depth versus lateral resolution and throughput for various metrology techniques.

Figure 5. 3D Metrology Landscape

Figure 6 summarizes the current readiness of 3D metrology to address various needs.

Figure 6. 3D Metrology Challenges

From figure 6 there are still a lot of challenges to overcome to achieve a comprehensive metrology program.

Conclusion

The era of High NA EUV is approaching. There is good progress being made in pellicles, photoresists, and metrology and imec continues to work in all three areas for further progress.

Also Read:

TSMC has spent a lot more money on 300mm than you think

SPIE Advanced Lithography Conference 2023 – AMAT Sculpta® Announcement

IEDM 2023 – 2D Materials – Intel and TSMC

IEDM 2022 – Imec 4 Track Cell

 


Ansys Acquires Another!

Ansys Acquires Another!
by Daniel Nenni on 05-16-2023 at 4:00 pm

Diakopto logo

The headline is: Ansys Signs Definitive Agreement to Acquire Diakopto, Expands Multiphysics Simulation Portfolio for Semiconductor Designers. The acquisition complements Ansys’ existing signoff solutions and enables integrated circuit (IC) designers to detect problems earlier in the design flow.

Which is certainly true but let me tell you what Diakopto really is, they are a diamond in the rough. A very large diamond. This is definitely one of those 1+1=3 types of situations, absolutely. Congratulations to John Lee and his Ansys M&A team on another amazing acquisition.

We have been working with Diakopto for less than a year but we have learned a lot about them. Starting with the CEO interview (Dr. Maxim Ershov) followed by a series of articles written by Maxim directly that earned an amazing amount of traffic.

Even though Diakopto was relatively young the customer list is most impressive with more than 30 companies using the tool. The only thing holding Diakopto back, in my opinion, was the sales and support channel which is no longer an issue with Ansys. Ansys has one of the strongest channels in EDA which is one reason why I enjoy working closely with them. Ansys and Diakopto also have very strong product synergy, which is highlighted below, thus the 1+1=3 reference.

Key Highlights
  • The addition of Diakopto’s solutions to Ansys’ portfolio will deliver a competitive edge to engineers using Ansys to create high-performance integrated circuits
  • Diakopto’s unique and market-leading products complement Ansys’ existing solutions – the combination will empower our customers to deliver optimal designs and accelerate time to market
  • The transaction is subject to the satisfaction of customary closing conditions and is expected to close in the second quarter of 2023

PITTSBURGH, May 16, 2023 /PRNewswire/ — Ansys, (NASDAQ: ANSS) the global leader and innovator of engineering simulation software, announced today that it has entered into a definitive agreement to acquire Diakopto. A provider of differentiated EDA solutions to accelerate integrated circuit (IC) development, Diakopto focuses on helping resolve critical issues caused by layout parasitics. The transaction is subject to the satisfaction of customary closing conditions and is expected to close in the second quarter of 2023. It is not expected to have a material impact on Ansys’ consolidated financial statements in 2023.

Ansys has entered into a definitive agreement to acquire Diakopto
Diakopto develops products that address the growing complexities and unintended effects of designing ICs in the modern era. Semiconductor designs increasingly employ advanced process node technologies, where interconnect parasitic effects limit the performance, reliability, and functionality of designs. Diakopto’s market-leading products have been adopted by dozens of customers, including tier-one semiconductor companies, for a broad range of applications.

With the acquisition, Ansys will better enable design engineers to “shift left,” and to detect interconnect parasitic problems early in the design cycle. Diakopto’s products provide actionable analytics to guide designers to fix these problems – a capability that has not existed before. Through early identification and what-if analysis of parasitic problems, engineers can minimize costly iterations late in the design cycle – furthering cost and time savings.

“Diakopto’s culture of strong engineering excellence and its innovative and highly differentiated products create a natural alignment with our organization. We are eager to welcome their team to the Ansys family,” said Shane Emswiler, senior vice president of products at Ansys. “Incorporating Diakopto’s unique methodology will support designers using Ansys to quickly and easily pinpoint the few elements, out of billions, causing bottlenecks. Designers can then optimize and debug designs more efficiently for enhanced IC performance and reliability, and accelerate time to market. The acquisition will complement Ansys’ existing offerings for engineers at every level as Diakopto’s intuitive and out-of-the-box experience doesn’t require extensive training or complicated setups or configurations.”

“Today’s announcement brings together two like-minded companies on the forefront of innovation, and we are excited about becoming part of the Ansys family,” said Maxim Ershov, CEO and CTO at Diakopto. “By joining forces with Ansys, we’re confident that we can solve a broader set of problems in the chip design workflow together, strengthening offerings for our customers and driving more innovations in high-tech designs for data center, 5G, automotive, and mobile applications.”

About Ansys

When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys.

Take a leap of certainty … with Ansys.

Ansys and any and all ANSYS, Inc. brand, product, service and feature names, logos and slogans are registered trademarks or trademarks of ANSYS, Inc. or its subsidiaries in the United States or other countries. Diakopto and ParagonX are trademarks of Diakopto Inc. All other brand, product, service and feature names or trademarks are the property of their respective owners.

Contacts
Media
Mary Kate Joyce
724.820.4368
marykate.joyce@ansys.com

Investors
Kelsey DeBriyn
724.820.3927
kelsey.debriyn@ansys.com

Also Read:

Multiphysics Analysis from Chip to System

Checklist to Ensure Silicon Interposers Don’t Kill Your Design

HFSS Leads the Way with Exponential Innovation


Join the AI Generated Open-Source Silicon Design Challenge!

Join the AI Generated Open-Source Silicon Design Challenge!
by Daniel Nenni on 05-16-2023 at 10:00 am

Join the AI Generated Open Source Silicon

As we all know design starts are the life blood of the semiconductor industry, both big and small. Enabling those design starts is what the semiconductor ecosystem is all about and Efabless has a very unique value proposition in this regard.

Efabless is a free cloud-based chip design platform, growing community of 9000+ chip designers, and fabrication friendly technology company that takes you from idea to silicon inside your product. Only Efabless chipIgnite provides a complete end-to-end solution for creating your own chip at a very low cost. Established in 2014, Efabless has a thriving community of thousands of chip designers putting more than 400 chips to fabrication.

I’m friends with the Efabless CEO and CTO and I have followed this journey since the beginning. As I well know building an online semiconductor design community is a very difficult thing. It is an underappreciated never ending job. Efabless however has done something very clever here and I see continued growth opportunities ahead, absolutely.

So let’s get to it, the contest:

Show the World how Innovation can Move from Prompt to Silicon in Record Time!

Generative AI offers the potential to accelerate chip innovation by putting chip design into the hands of more people than ever before and enabling them to design faster and for less cost.

In this Challenge, we aim to show how a community can use this powerful new tool to deliver interesting designs in a matter of weeks.

Award:

Be among one of the first to design and tapeout an AI generated open-source silicon design. Participants will be eligible to win free fabrication for their design and receive public recognition and promotion of their design by Efabless.

Requirements:

All designs will be judged by a panel of experts who share a lifelong commitment to electronics and believe in the power of AI and machine learning to drive innovation. Stay tuned for more details!

Judging Criteria:

– Project Documentation
– Prompt Documentation
– Code
– Verification Coverage
– Technical Merit
– Community Application Interest Poll
– All requirements must be met to be eligible to win
– All submission content, documentation, prompt must be in English
– A short description of the project must be included with your design. It will be used for introducing your idea in the community poll.
– All designs must be implemented and fit in the Caravel User Project area.
– The Verilog for the design must be coded by AI.
– Verification may be done outside of the AI environment but verification testbenches must be provided as a reproducible element of this process.
– All prompts or auto GPT session logs used in the design must be provided as part of the deliverables for the design.

The design needs to be open source with all materials required to reproduce made public.

The design must be implemented using the OpenLane chipIgnite flow including all configuration and run results.

Must have testbenches for RTL verification as well as constraints for STA and SDF simulations.

Must be implementable in SKY103 with available standard cells and DFFRAM and not require open RAM or other discrete memories for implementation.

The design must pass precheck and tapeout submissions on the eFabless platform.

Winners will be expected to provide a video and screenshots demonstrating the creation of the project in a how-to or step-by-step format. These materials may be used by eFabless for promotional purposes.

Official Rules

-Eligibility

Participants must be able to receive silicon and parts shipped from the United States. As such, members of United States embargoed or sanctioned countries are not eligible to participate. Current employees of Efabless or their family members are also not eligible to participate.

-Deadline

The submission deadline is Friday, June 2, 2023 at 11:59 pm PT.

-Sponsorship

The contest is sponsored by Efabless Corporation, 165 University Ave, Palo Alto, CA 94301

-Agreement to Official Rules

Participation in the contest constitutes participant’s full and unconditional agreement to and acceptance of these Official Rules and the decision of the Sponsor, which are final and binding.

An entry may be rejected at the sole and absolute discretion of Efabless.

By entering the contest, you agree and allow Efabless to use, display, and publish a winner’s identity, including their name and photo, in promotional materials. The participants also agree that Efabless has the right to use participant’s designs and other material in sales and marketing.

How to Enter

Register on the Efabless platform if you have not already done so.

Submit your entry by including all content on a public GitHub repo.

Create a public project for the chipIgnite 2306Q shuttle using the GitHub repo from the previous step.

Submit success precheck and tapeout jobs for your design.

Complete the remainder of the billing and shipping information as well as terms and export agreements. You will not be charged or invoiced for your submission. Complete the final submission for the project on the platform.

Send an email to shuttle@efabless.com with a link to your project.

Limit one entry per person, per email address. Your entry must be original.

Note: If you have not received permission to use copyrighted material, you may not include the material in your entry.

Contest Winner Announcement

Contest winners will be announced on Friday, June 9 2023. The winner will be provided fabrication at no cost in the June 5th chipIgnite shuttle, 2306Q.

Contact

Please contact shuttle@efabless.com if you have any questions about this contest: https://efabless.com/ai-generated-design-contest

Also Read:

A User View of Efabless Platform: Interview with Matt Venn

CEO Interview: Mike Wishart of Efabless


Emerging Stronger from the Downturn

Emerging Stronger from the Downturn
by Kalar Rajendiran on 05-16-2023 at 6:00 am

Full Flow from HL Synthesis through to GDSII Accelerates the creation of AI IP

It was refreshing to hear a talk focused on emerging stronger from the downturn when the news and media are focused on the gloom. At the recent Siemens EDA User2User conference, Joe Sawicki, executive vice president, IC, gave an uplifting keynote talk to the audience. He highlighted a secular growth trend happening in the semiconductor industry, what is driving that trend, and what EDA’s role is to support and drive this growth. Joe finished his keynote by identifying the thrust of Siemens EDA’s R&D efforts and providing a couple of examples.

Here is a high level synthesis of Joe’s keynote presentation.

Historically speaking, the semiconductor market has been a cyclical market with the memory market segment having an oversized influence on the overall market growth. Cyclical trends are affected by the boom and bust swings of the market. A secular trend on the other hand is one that is likely to continue moving in the same general direction for the foreseeable future.

Drivers Behind the Secular Trend

The worldwide aggregate data traffic growth rate is 2x per year with the data being created, transmitted, processed and stored by semiconductor devices. Semiconductors are taking a more important role than ever. This is reflected by statistics that show how the semiconductor content share of system product value has grown over the last few decades. From an average of 8.3% until the late 1980s to 16% until mid 2010s, it has reached 25% now and projected to go up. More and more intelligence is being built into systems. Systems companies have noticed this and getting directly involved in System-on-Chip (SoC) designs and tapping pure-play foundries. This is to ensure optimization of profitability of their systems and for the differentiated use of intelligence-driving technology into their products. The above are the drivers behind the secular growth trend for semiconductors. The number of design starts are projected to continue to grow at 5% driven by many new growth applications. Market Research firm IBS is predicting that artificial intelligence (AI)-driven semiconductors are going to be the major market driver behind the growth to the trillion dollar mark.

Three Pillars of Siemens EDA R&D Investment

Siemens EDA is focusing on three pillars of R&D investment to support the secular growth trend.

Technology scaling – supporting transistor scaling, silicon manufacturing processes, variability analysis of designs.

Design scaling – extracting more functionality and performance from the designs themselves on top of what the doubling of transistors every two years.

System scaling – system complexity is growing at a much faster rate than 2x. Understanding how a system will respond over time which in turn requires an understanding of how the ICs will respond over time. Looking at new ways of system level verification to help build better designs to solve the end customers’ needs. For example, autonomous vehicle systems or other IoT based systems.

An area that cuts across all three pillars is the system technology co-optimization (STCO) for 2.5D and 3D ICs. Multiple Dies into one package in an optimal way to meet the cost, power, thermal and performance goals is not an insignificant challenge.

How Does Siemens EDA Support the Secular Growth Trend

At Joe’s keynote was time-compressed to accommodate time for two more keynote talks, I followed up to gain additional context and insights for this post.

For a 10 year (2020-2030) CAGR for semiconductors, Market Research firm IBS [Report: May 2022] is projecting a 32.4% for semiconductors with AI content compared to a meagre 3.3% CAGR without. While the AI hardware will be the critical driver for applications and semiconductor volume, off-the-shelf IP will be insufficient to address power and performance. The ability to create unique AI silicon content rapidly is challenging but also a critical success factor for the next generation of applications. That is why, design scaling and system scaling are taking on even more importance going forward.

In the design scaling category, the areas of focus include creation of high-quality RTL, advanced digital implementation for out-of-the-box PPA, data-driven verification and end-to-end test solutions.

As an example, High-Level synthesis through GDSII (Siemens EDA Catapult) enables accelerated creation of unique AI IP. The premise is that moving the design to even higher level than RTL, say to C-level approach enables much more architectural exploration to be achieved.  For example, analyzing the effects of varying bit widths, memory structures, etc. Integrating the results from these analysis into a detailed place and route environment makes it possible for very good prediction of overall performance.

As for system scaling category, execution of system software on the SoC is critical. And so are the integration and validation within the system context to ensure the correct operation of complex systems. The scope of what Siemens EDA brings to its customers to support their system scaling requirements is immense.

Following is an automotive system example that Joe shared during his talk. It takes sensing and traffic data, connects to a decision framework and then to an actuator braking system. The breadth and depth of the processing and Multiphysics analysis to be performed to simulate an accident scenario in a metaverse city environment is tremendous. Siemens EDA customers are able to get these capabilities under one roof. Siemens PAVE360 is one such demonstration. PAVE360 is a complete autonomous verification and validation environment modeled as a system that represents a twin image of the physical vehicle and its driving surroundings. Siemens PAVE360 powers the needs of OEMs and suppliers to explore, design, build and train/validate compute solutions critical to the future of connected and autonomous driving cars.

Summary

The semiconductor industry has become a central point in the awareness of most governments around the world with the tail wind likely to further strengthen the secular trend presented by Joe. During the User2User conference, many customers provided substantiation of how Siemens EDA’s various tools and solutions are addressing their market requirements and the secular growth trends. SemiWiki will be posting separate blogs on many of these presentations.

To learn more about everything Siemens EDA has to offer, visit this page.

Also Read:

Tessent SSN Enables Significant Test Time Savings for SoC ATPG

Using ML for Statistical Circuit Verification

Achieving Optimal PPA at Placement and Carrying it Through to Signoff


Overcoming Semiconductor Supply Chain Bottlenecks

Overcoming Semiconductor Supply Chain Bottlenecks
by Daniel Payne on 05-15-2023 at 10:00 am

supply chain, PLM and IPLM

During the recent COVID pandemic it was common to read about automobile companies unable to deliver new vehicles, caused by the shortage of specific automotive chips. Even bad weather has shut down the supply of semiconductor parts to certain customers. This disruption of the IC supply chain has caused many companies that buy and use semiconductors to consider moving some of their chip designs to in-house programs. A recent white paper from Methodics addressed the challenges of in-house chip design.

Success stories of systems companies doing their own chip designs include Apple, Tesla, NVIDIA, Qualcomm and Broadcom. Designing ICs along with their embedded software requires experience and best practices. Many components of ICs are building blocks called IP, and there’s a whole ecosystem to choose from pre-built, common functions, like: Radios (Bluetooth, WiFi), RAM, ROM, Processors, USB, etc.

Semiconductor design also has risks and high costs from both the EDA software for design and photomasks involved in fabrication. Calculating the ROI at the very start of an IC project is required, and using an IP-based approach is a best practice. Modeling your new IC as IP blocks allows your engineering group to compare in-house development versus purchasing IP from a third party. Planing and tracking all IP is foundational to model costs and track development progress.

The Methodics recommended methodology is to start with a planning Bill of Material (BoM) to evaluate tradeoffs and perform analysis. Using a general-purpose Product Lifecycle Management (PLM) tool for 3rd party semiconductor components, and a semiconductor planning BoM tool for the in-house chip design, enables you to compare each approach.  The combination of PLM and Methodics IP Lifecycle Management (IPLM) tools is shown below, as part of the build or buy decision process to improve your supply chain.

Perforce Methodics IPLM Planning BoM

The Planning BoM has all of the details for each hierarchical IP being used, along with version history as each IP goes through a release cycle. Your team transitions from using the Planning BoM to an execution BoM while using the Perforce IPLM.

Execution BoM

The IP hierarchy is defined in the Execution BoM and it should support popular data management tools like Git or Perforce Helix Core. Any version conflicts need to be automatically identified in both hardware and software IPs to keep compatibility.

Multiple DMs

Both hardware and software IPs are managed in this approach, making sure that requirements can be traced for every component. You will know which software component is delivered for each hardware component, ensuring transparency.

Release engineers are tasked with tracking each release candidate and managing the integration process, and using Methodics IPLM automates the manual integration and curation processes.

Meta-data can be used during the design process to account for ISO 26262 functional safety compliance requirements per IP. Traceability of requirements to IP blocks is captured with Methodics IPLM. Even security meta-data can be added on the IP or component hierarchy to help asses the security threats for each project, as you reference an internal IP Security Assurance (IPSA) catalog of issues for a circuit.

Summary

Systems companies are gradually adopting in-house IC design projects as a means to reduce supply chain bottlenecks. Using an IP-centric methodology is a best practice to control your ROI and start building IP re-use. The Methodics IPLM platform has been around for many years, helping to manage the challenges of IP-based design across entire corporations.

Benefits of this approach are: traceability of requirements, managing IP re-use, having a centralized catalog of all IP – hardware and software, having both planning and platform BoMs, and having analytics to see where you are at.

Read the entire nine page White Paper online here from Methodics.

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