Aleksandr Timofeev is CEO and Founder of POLYN Technology, an innovative provider of ultra-low-power high-performance NASP (Neuromorphic Analog Signal Processing) technology. Alexander is a serial entrepreneur with more than 20 years in the high-tech industry. Prior POLYN, he founded iGlass Technology, a company that developed novel electrochromic smart glass technology. He built the core team, general technology, and product concept and successfully sold the company at the end of 2020 to a strategic investor. Aleksandr is also founder and managing partner at FPI VC team, an early-stage venture investment management company. The fund focuses on early-stage innovative companies, developing clear product concepts and strategies and working with venture firms and partners for subsequent funding rounds.
While looking at the landscape of new startups in the AI/ML industry I found POLYN. The company differs from others in its business model as well as its concept and technology approach.
POLYN is a fabless semiconductor company selling ready-to-use Analog Neuromorphic chips as Application Specific Standard Products, targeting specific technological challenges in huge and fast-growing markets, particularly wearables, connected health, and Industry 4.0. Founded in 2019, it is registered in the UK with HQ in Israel.
According to its website, POLYN offers two products, and one more is under development. Recently it was announced that POLYN was accepted into the Silicon Catalyst incubator family.
We talked with Aleksandr Timofeev, CEO and founder, to explain the technology and what he is up to now. We asked Aleksandr’s opinion on today’s neuromorphic computing, what is special about POLYN, and how far we are from a real Tiny AI solution working on the sensor level. Here’s the interview:
Q: First, congratulations on joining the Silicon Catalyst incubator Could you say few words about what is in it for POLYN?
AT: POLYN’s objective as a fabless semiconductor company focusing on ready-to-use analog neuromorphic chips is to collaborate with leading semiconductor vendors, industry partners, and entrepreneurs. Our mission is to introduce novel analog neuromorphic solutions for wearables, hearables, and IIoT on-sensor pre-processing with highly efficient energy per inference ratio. By being part of the Silicon Catalyst community and its huge portfolio of partners, we expect to accelerate our plans to improve cost, time to market, and the reach of our unique technology.
Q: I see your company decided to go a different way with constructing a chip from a neural network, unlike many others who are developing general purpose processors to apply a neural network there?
AT: Yes, we decided that for a neuromorphic based product it is more efficient to synthesize a chip from a neural network model, not like in the digital domain where you have fixed, general purpose PU instruction sets, and different software applications using them. When you start training a neural network (NN), you don’t know what final size you will get. If you have a fixed neuromorphic core, for some NNs it will be too small, and for others too big.
Q: Ok, interesting, but that means you need to generate a lot of chipsets and that would be both time and cost consuming. How you are dealing with that challenge?
AT: We are focused on the ASSP model. Our chip is related to sensor or signal type, but not a sensor model. For example, our Voice Extraction NASP chip works with any type of analog or digital mems microphone and other signal sources. And we will generate a new NASP core only for a new sensor or signal type. As you understand, it covers millions of products. In case some new product moves to a different physical device, we can upgrade the chip easily, thanks to our fully automated process. So, to summarize, first NASP is application-specific and not product-specific, so the volumes are huge. Second, moving from application to application is easy with the POLYN automation tools. By the way, our tools were the first technological achievement at the beginning of the company, and they remain a unique EDA instrument for neural network conversion.
Q: Very impressive, but I have another question: Your critics could say that implementing even the inference neural network models requires changes, and as a result your neural network will need tuning from time to time. If your technology is implemented in a fixed resistor layer, how do you support neural network changes and updates?
AT: First, we use the fundamental property of a neural network: when you train a deep neural network, after a few hundred training cycles a major part of the layers will become frozen. So typically, about 90% of layers are not changing anymore, and are not involved in the following updates. Only a few last layers require an update if you need to change the classification. In such case we use a hybrid solution: the 90% layers are converted into a high performance NASP core and the last 10% remain in the flexible digital domain. But it is important to remember that our solution is focused on sensor level applications. We are not simulating brain functions, where constant learning (or re-training) is critical. In many sensor-level applications the pre-processing task is fixed and doesn’t require any update.
Q: Let’s discuss the analog part. I mean, who would imagine we come back to analog after getting digital with millions of transistors on a chip and talking today about 2nm process? Why do you think analog is a right option for complex math models as neural networks?
AT: First of all, we talking about neuromorphic analog, which is not like old style analog computers. We represent a trained neural network using analog neurons. The fundamental property of this structure is true parallel data processing.
Any digital system has step-by-step execution. But the human brain, one of the most power-efficient computation devices, uses parallel data processing. It is important to note that POLYN is mimicking not the central brain but peripheral systems. We are at the sensor level where the main idea is pre-processing, removing noise, extracting data, and here the analog is irreplaceable. Digital can go down in the process, but for Joule per Inference ratio, analog will win.
Q: Any more arguments for analog? F
AT: First of all, we are talking about neuromorphic analog, that represents a trained neural network using analog neurons. The fundamental property of this structure is true parallel data processing.
Any digital system has step-by-step execution. But the human brain, one of the most power-efficient computation devices, uses parallel data processing. It is important to note that POLYN is mimicking not the central brain but peripheral systems. We are at the sensor level where the main idea is pre-processing, removing noise, extracting data, and here the analog is irreplaceable. Digital can go down in the process, but for Joule per Inference ratio, analog will always win.
Q: Any more arguments for analog? For example, how do you resolve the analog implementation noise issue? What is the product deviation on the math model?
AT: The answer again lies in the term “neuromorphic,” as neural networks are implemented in a neuromorphic analog circuit. The point is that resilience to errors is a fundamental property of neural networks, and training increases the resilience.
Circuit non-idealities can be divided into two groups: random and systematic errors.
Systematic errors occur because a typical circuit implementation only approximates an ideal signal processing operation to a limited extent. Such errors are caused, for instance, by the non-linear operating characteristics of devices or by finite gain of an analog amplifier.
Stochastic errors may happen during the fabrication of integrated circuits and result in a random variation of the properties of the fabricated on-chip elements. These errors, however, can be modelled and addressed during development. For example, the mismatch between neighboring elements is usually much smaller than the variation of parameters’ absolute values. Therefore, differential architectures could significantly improve precision.
For an analog circuit design, it is important that such errors do not accumulate. For this, the neural networks are trained using special technology for error compensation
Q: Interesting. Could tell us about the birth of POLYN and the idea of your technology?
AT: I met Dmitry Godovsky, our Chief Scientist, at the end of 2018. Dmitry worked eight years previously on a new math model of converting a digital neural net to a new implementation. After few months of discussion, we understood that this new model can be represented as a neuromorphic analog circuit. So, in April 2019 we launched POLYN Technology. Since then, we have constantly invested in know-how and innovation. Today we have 25 patents for the technology and products.
Q: Naturally, this raises the question: what about FABs? Could they run the fabrication immediately, or they need to adapt their processes? By the way, the same question applies for the PDK and EDA tools you are using for the chip development.
AT: Our strong advantage is that we are using any standard process in 40-65 nm range and can align our product libraries to any standard PDK. Our NASP compiler and physical design module work on top of existing standard EDA-based design flow. The output is a GDSII file ready for tape out immediately. Together with that we have developed our design as a BEOL, so the resistor layer is mask programmable and could be replaced independently to optimize cost and time to market. The EDA tool, we call it T-Compiler, is important for time to market today and for our business model in the future. Right now, we are selling chipsets and IP Blocks. By the way, we also see that the market of chiplet solutions could be covered, since SiPs (systems in package) are becoming increasingly these days.
But once the technology is proven and more customers see the advantage of NASP for medium and higher volume products, then our T-Compiler tool will be a part of our business model, enabling generation of application-specific Neuromorphic Analog chips for specific tasks.
Q: Great clarification, thanks. Let’s now talk in general about when you think it makes sense to convert a neural network into silicon. What applications are you covering by the NASP solutions?
AT: We focus on any type of one-dimensional signal preprocessing, such as voice, health care sensors, accelerometer, or vibration sensors. And some of our solutions you can evaluate already with simulation that enables evaluation of the chip before its synthesis, to reduce the chance of unexpected behavior. Anyone who is looking for always-on smart sensor data pre-processing is more than welcome to contact us and get access to our D-MVP simulation model. For example, voice extraction and voice detection for hearing assistance demos are functions and running already. So, customer can evaluate and start the design in advance to be ready when the first chip will come from the factory by Q2 of 2023. Customers can also influence the functionality if they are in time to catch the last changes, we are doing these days.
Q: And what is your product strategy?
AT: Three directions are in our scope of activities for 2023, wearables, hearables, and vibration monitoring for predictive machine maintenance. The first product is planned for mid-2023 and it is our voice extraction solution we announced a week ago. The name of the product line is NeuroVoice and it is intelligent voice extraction and processing for the next generation of smartphones, earbuds, hearing aids, microphones, smart speakers, and intercoms. POLYN’s NeuroVoice NASP chip solves the problem of communication in a noisy environment. This differs from noise cancellation and can answer such challenges as irregular noises like animal sounds, babies crying, and sirens. It also solves the problem if the sound comes over the network already mixed with noise. Together with voice extraction, NeuroVoice offers a combination of voice management features such as voice activity detection, keyword spotting, and others. In addition, the product can be customized for special requirements.
Q: Was it easy to raise money? I know that the situation changes every time.
AT: Raising money is never easy (smiling). Of course, we worked hard to communicate with investors. We have a few VCs joining us and several more currently in the due diligence process. That is where we anticipate value in joining the Silicon Catalyst incubator, with the increased exposure we will gain through the incubator’s huge portfolio of partners.
Q: What do you think about neuromorphic chips today? Those like Intel Loihi, BrainChip and others around?
AT: We can discuss other solutions and compare performances, but in general, I can say that in our opinion they are targeted to a more centric position on the edge, with power consumption of a hundred milliwatts to a few watts, but POLYN is focused on the micro-watt level of the thin edge.
Q: And the final question. As a visionary, how do you see the neural-network- on-chip market and ways of its development? Would it be digital, in-memory, or similar to NASP?
AT: For some time, I think, things will run in parallel, and each technology will try to find niches, but finally, in my opinion, the future lies in self-organizing structures, like NASP, but with different physical principles of neurons.
Q: On that note, thank you very much, Aleksandr.
AT: Thanks a lot for the opportunity, and let’s meet in mid-2023 when the first NeuroVoice chip will roll off the line.
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