SemiWiki – Page 129 – The Open Forum for Semiconductor Professionals

May 30, 2023October 4, 2023

Coherent Optics: Synergistic for Telecom, DCI and Inter-Satellite Networks

Coherent Optics: Synergistic for Telecom, DCI and Inter-Satellite Networks
by Kalar Rajendiran on 05-30-2023 at 10:00 am
Categories: Alphawave Semi, IP

The telecommunications industry has experienced significant growth in recent years, driven by the increasing demand for high-speed internet and data services. This growth has created a surge in traffic on optical networks, leading to the development of new telecom network architectures that can support the increasing demand for bandwidth.

Optical networking technologies, such as coherent optics, have traditionally been developed for telecom applications. However, with the growth of hyperscale data centers and the increasing demand for high-speed networking, these technologies are now also being adopted in data center applications. Traditionally, data centers have used copper or short-range optical cables to connect servers and storage devices within the same data center. However, as data volumes continue to grow and data center interconnect (DCI) requirements increase, coherent optical networking is becoming an attractive option for data centers. With coherent optical networking, data centers can achieve higher data transmission rates over longer distances, resulting in increased data capacity and lower latency. 400G was the first data rate where hyperscale data center applications outpaced telecom applications in the use of coherent optics.

Coherent optics enables the transmission of high-speed data over long distances by using advanced signal processing techniques to mitigate the effects of signal distortion and noise. This technology is essential for supporting the growing demand for high-speed internet and data services, particularly in areas where traditional copper-based networks are not feasible. This trend is likely to continue and proliferate further going forward, driven by the ongoing growth of cloud computing, big data, AI/ML workloads and other data-intensive applications.

Another driver of the shift towards optical interconnects has been the increasing complexity of satellite networks. As satellite networks become more complex, the need for high-speed, low-latency communication between satellites becomes more important. Optical interconnects are ideal for this type of communication, as they offer very low latency and can support high-speed data transfer between satellites.

Optical Telecom – Satellite Communications Synergies

Optical telecom synergies have played a significant role in the evolution of inter-satellite communication. Many of the technologies and techniques used in optical telecom networks have been adapted for use in inter-satellite communication. Innovations in optical digital signal processing (DSP) and system automation also offer several optimization opportunities with inter-satellite interconnects.

Improved Signal Quality: Optical DSP can be used to compensate for impairments in the optical signal, such as chromatic dispersion and polarization mode dispersion. This can improve the quality of the signal and reduce the bit error rate (BER), enabling high-quality communications over long distances.

Reduced Latency: System automation can also be used to optimize the routing of data between satellites, minimizing the number of hops and reducing latency. This can improve the responsiveness of the system and enhance the user experience.

Power-efficient Modulation Formats: Optical DSP can enable the use of power-efficient modulation formats, such as pulse-amplitude modulation (PAM), which can reduce the power consumption of the inter-satellite links while maintaining high data rates.

Energy-efficient Signal Processing: Optical DSP can also be optimized to perform signal processing operations more energy-efficiently. For example, parallel processing and low-power digital signal processing techniques can reduce the power consumption of the signal processing circuitry.

Interoperability Demonstration

At the recent Optical Fiber Communication (OFC) conference, Alphawave Semi showcased its ZeusCORE XLR test chip during the interoperability demonstration organized by the Optical Internetworking Forum (OIF). Alphawave Semi executives Loukas Paraschis, VP of Business Development and Tony Chan Carusone, CTO, presented on high-speed connectivity leadership. Their presentations touched on the growing synergies and optimization opportunities of inter-satellite interconnects and optical telecom through innovations in optical DSP and system automation.

Summary

As the volume of data traffic on optical networks continues to increase, it is essential to ensure that the cost of implementing and maintaining these networks remains affordable. This requires a delicate balance between increasing volume and decreasing costs, which can only be achieved through innovation and the development of highly-integrated co-designed solutions. These solutions combine multiple technologies and functions into a single device, reducing the complexity and cost of optical network infrastructure. This approach enables the development of more efficient, cost-effective optical networks that can meet the growing demand for bandwidth and high-speed data transmission.

To learn more about the ZeusCORE, visit the product page.

Also Read:

Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications

Alphawave Semi at the Chiplet Summit

Alphawave IP is now Alphawave Semi for a very good reason!

May 30, 2023June 16, 2023

Deep Learning for Fault Localization. Innovation in Verification

Deep Learning for Fault Localization. Innovation in Verification
by Bernard Murphy on 05-30-2023 at 6:00 am
Categories: AI, Cadence, EDA

A new look at fault localization and repair in debug using learning based on deep semantic features. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Improving Fault Localization and Program Repair with Deep Semantic Features and Transferred Knowledge. The authors presented the paper at the 2022 International Conference on Software Engineering and are from Beihang University in Beijing and Newcastle University in New South Wales.

The method goes beyond familiar spectrum-based (SBFL) and mutation-based (MBFL) localization techniques to use deep learning from pre-qualified datasets of bugs and committed fixes. The fix aspect is important here because it depends on very accurate localization of a fault (in fact localization and nature of the fix are closely linked). The paper uses SBFL and MBFL metrics as input to their deep learning method. The authors demonstrate their methods are more effective than selected SBFL and MBFL approaches and argue this is because other methods have either no semantic understanding or only a shallow understanding of semantic features of the design, whereas they intentionally have a deeper understanding.

Fully automatic repair might be a step too far for RTL debug, however suggested fixes are already familiar for spell and grammar checks, hinting that this feature might also be valuable in verification.

Paul’s view

One year on from our review of DeepFL, we take a look at another paper that tries to move the needle further. Automatic bug detection is now a regular topic with Cadence customers and expectations are high that deep neural networks or large language models can be used to dramatically improve time spent root causing bugs.

DeepFL used a RNN to rank code for bugs based on suspiciousness features (complexity-based, mutation-based, spectrum-based, text-based). This month’s paper adds an additional bug template matching step as a further input feature to improve accuracy. The bug template matcher is itself another RNN that matches individual code statements to one or more of 11 possible bug templates, e.g. a missed null pointer checker, incorrect type cast, incorrect statement position, or incorrect arithmetic operator.

The key contribution of the paper for me is the dataset the authors build to train their bug template matching network. They mine the entire github repository to find real bug fixes that match their bug templates. For each match they require that there be another matching statement elsewhere in the same source code file that is not part of the bug fix – i.e. so the dataset has both positive and false-positive matches. The final dataset has around 400,000 positive/false-positive bug fix pairs. Nice!

As with DeepFL, the authors benchmark their tool TRANSFER-FL using Defects4J. Results look decent – 171 of the 395 bugs in Defects4J are ranked Top-5 by TRANSFER-FL vs. 140 using DeepFL. However, from a commercial standpoint 171 is still less than half of the total 395 benchmark set. If you look at the average rank across all 395 it’s 80, a long way from Top-5, so a ways off commercial deployment. I’m looking forward to reviewing some large language model-based papers next year that move the needle yet further 😊

Raúl’s view

This month we move into the areas of fault localization and automatic program repair for SW, the reviewed paper explores these techniques for Java code. In May 2022 we reviewed DeepFL, which is similar to this paper in that it extends traditional spectrum- and mutation-based techniques for fault localization with deep learning models.

To state my conclusion upfront, perhaps automatic RTL or SystemC fault localization and code repair will become routine in the foreseeable future… The authors are optimistic regarding the applicability to other languages, “most of the fix templates can be generalized to other languages because of the generic representation of AST (Abstract Syntax Tree)” with the caveat that sufficient data needs to be available for training the different networks used in their approach. For the paper 2000 open-source Java projects from GitHub were collected to construct 11 fault localization datasets with a total of 392,567 samples (faulty statements for 11 bug types that have a bug fix commit); and a program repair dataset with 11 categories of bug fixes with a total of 408,091 samples, each sample consisting of a faulty statement with the contextual method and its corresponding bug type. An AST is used to do this matching.

The detailed approach, called TRANSFER, is rather complex and requires some time to digest, 67 references help to dive into the details. It leverages existing approaches for fault localization, 1) Spectrum-based features which take source code and relevant test cases as inputs and output a sorted list of code elements ordered by suspicion scores calculated from the execution of test cases, and 2) Mutation-based features which calculate suspicion scores by analyzing the changes of execution results between original code element and its mutants. It adds 3) Deep Semantic features obtained by using BiLSTM (Bidirectional Long Short-Term Memory) binary classifiers trained with the fault localization datasets. Program repair is done using a “fine-tuned” multi-classifier trained with the program repair dataset.

The bottom line is that TRANSFER outperforms existing approaches, successfully fixing 47 bugs (6 more than the best existing approaches) on the Defects4J benchmark.

Writing and debugging SW is already routinely assisted by AI such as GitHub Copilot; designing hardware, aka writing RTL or higher-level code, can’t be too far behind, perhaps the largest obstacle being the availability of the data required.

Also Read:

Opinions on Generative AI at CadenceLIVE

Takeaways from CadenceLIVE 2023

Anirudh Keynote at Cadence Live

May 29, 2023May 30, 2023

WEBINAR: An Ideal Neural Processing Engine for Always-sensing Deployments

WEBINAR: An Ideal Neural Processing Engine for Always-sensing Deployments
by Daniel Nenni on 05-29-2023 at 10:00 am
Categories: Events, Expedera, IP

Always-sensing cameras are a relatively new method for users to interact with their smartphones, home appliances, and other consumer devices. Like always-listening audio-based Siri and Alexa, always-sensing cameras enable a seamless, more natural user experience. However, always-sensing camera subsystems require specialized processing due to the quantity and complexity of data generated.

But, how can always-sensing sub-systems be architected to meet the stringent power, latency, and privacy needs of the user? Despite ongoing improvements in energy storage density, next-generation devices always place increased demands on batteries. Even wall-powered devices face scrutiny, with consumers, businesses, and governments demanding lower power consumption. Latency is a huge factor as well; for the best user experience, devices must instantly react to user inputs, and always-sensing systems cannot compete with other processes which add unneeded latency and slow reasons. Privacy and data security are also significant concerns; always-sensing systems need to be architected to securely capture and process data from the camera without storing or exposing it.

So how can always-sensing be enabled in a power, latency, and privacy-friendly method? While many existing Application Processors (APs) have NPUs inside of them, those NPUs aren’t the ideal vehicle for always-sensing. A typical AP is a mix of heterogeneous computing cores, including CPUs, ISPs, GPU/DSPs, and NPUs. Each processor is designed for specific computing and potentially large processing loads. For example, a typical general-purpose NPU might provide 5-10 TOPS of performance, with a typical power consumption of around 4 TOPS/W and about 40% utilization. However, it is inefficient because it must be somewhat overdesigned to handle worst-case workloads.

Always-sensing neural networks are specifically created to require minimal processing, typically measured in GOPS — GOPS being one-thousandth of TOPS. While the NPU in an existing AP is capable of always-sensing AI processing, it’s not the right choice for various reasons. First, power consumption will significant, which is a non-starter for an always-on feature since it translates directly to reduced battery life. Second, since AP-based NPU is typically busy with other tasks, other processes can increase latency and negatively impact the user experience. Finally, privacy concerns essentially preclude using the application processor. This is because the always-sensing camera data needs to be isolated from the rest of the system and must not be stored within the device or transmitted off the device. This is necessary to limit the exposure of that data and reduce the chances of a nefarious party stealing the data.

The solution, then, is a dedicated NPU specifically designed and implemented to process always-sensing networks with an absolute minimum of area, power, and latency: the LittleNPU.

In this webinar, Expedera and SemiWiki explore how a dedicated always-sensing subsystem with a dedicated LittleNPU can address the power, latency, and privacy needs while providing an incredible user experience.

REGISTER HERE

Presented by
Sharad Chole, Expedera Chief Scientist and Co-founder

About this talk
Always-sensing cameras are emerging in smartphones, home appliances, and other consumer devices, much like the always-listening Siri or Google voice assistants. Always-on technologies enable a more natural and seamless user experience, allowing such features as automatic locking and unlocking of the device or display adjustment based on the user’s gaze. However, camera data has quality, richness, and privacy concerns which requires specialized Artificial Intelligence (AI) processing. However, existing system processors are ill-suited for always-sensing applications.

Without careful attention to Neural Processing Unit (NPU) design, an always-sensing sub-system will consume excessive power, suffer from excessive latency, or risk the privacy of the user, all leading to an unsatisfactory user experience. To process always-sensing data in a power, latency, and privacy-friendly manner, OEMs are turning to specialized “LittleNPU” AI processors. In this webinar, we’ll explore the architecture of always-sensing, discuss use cases, and provide tips for how OEMs, chipmakers, and system architects can successfully evaluate, specify, and deploy an NPU in an always-on camera sub-system.

REGISTER HERE

About Expedera
Expedera provides scalable neural engine semiconductor IP that enables major improvements in performance, power, and latency while reducing cost and complexity in AI-inference applications. Third-party silicon-validated, Expedera’s solutions produce superior performance and are scalable to a wide range of applications from edge nodes and smartphones to automotive and data centers. Expedera’s Origin™ deep learning accelerator products are easily integrated, readily scalable, and can be customized to application requirements. The company is headquartered in Santa Clara, California. Visit expedera.com

Also Read:

Deep thinking on compute-in-memory in AI inference

Area-optimized AI inference for cost-sensitive applications

Ultra-efficient heterogeneous SoCs for Level 5 self-driving

CEO Interview: Da Chuang of Expedera

May 29, 2023July 18, 2025

Why Secure Ethernet Connections?

Why Secure Ethernet Connections?
by Daniel Payne on 05-29-2023 at 6:00 am
Categories: EDA, IP, Synopsys

While web browsing I constantly glance for the padlock symbol to indicate that the site is encrypting any of my form data by using the https prefix, which means that an SSL (Secure Sockets Layer) certificate is being used by the web hosting company. I have peace of mind knowing that my credit card information cannot be easily stolen on secure web sites using an SSL certificate. For Ethernet networks there are also several potential security breaches:

Man-in-the-middle attacks
Eavesdropping
Denial of service
Privilege escalation

The downside risks of data theft are quite high to any organization, and being compliant with data security standards like Health Insurance Portability and Accountability Act of 1996 (HIPAA) in the US and the General Data Protection Regulation (GDPR) are important.

To detect and prevent any unwanted data intrusions a system must have privacy measures like source validation and authentication.

Secure Ethernet Protocol

Thankfully, the IEEE created the Media Access Control Security (MACsec) protocol in 2006 to help secure Ethernet networks. The cryptography used to protect Ethernet traffic in MACsec is Advanced Encryption Standard-Galois/Counter Mode Cryptography (AES-GCM), also used for CXL and PCI Express security. MACsec is applied at Layer 2 of the Open Systems Interconnection (OSI) networking model, enabling data integrity, confidentiality, replay protection and data origin authenticity.

MACsec uses AES-GCM cryptography

The encrypted connection with MACsec has several authentication steps:

A Pre-Shared Key (PSK) for mutual peer authentication.
A secure Connectivity association Key Name (CKN) is exchanged.
The two endpoints decide which is the key server, and key client.
The key server sends the Secure Association Key (SAK) to the key client.
Encrypted data is ready for exchange.

You could take the time to become an expert on MACsec and design your own Ethernet security solution that conforms to the protocol, or consider using Ethernet IP from Synopsys that in addition to controllers and PHYs includes their MACsec Security Modules. Here’s what the Ethernet security IP from Synopsys looks like:

Synopsys Ethernet Solution with MACsec security

The benefits of using the Synopsys MACsec Security Modules include compliance with the IEEE 802.1AE standard, throughput scalability and configurability to tune solutions for specific applications and use cases with optimal latency, power, performance and area.

Synopsys not only has secure IP for Ethernet, it also extends into other interfaces: PCIe, CXL, USB, HDMI, DisplayPort, DDR, LPDDR, Die-to-Die, MIPI, UFS and eMMC.

Synopsys Secure Interfaces Solutions

Kalar Rajendiran wrote more about this topic in his January blog on SemiWiki.

Summary

Having a secure Ethernet makes a lot of sense, and with the IEEE protocol MACsec there’s a standard way to ensure that network data is not stolen or compromised. Malicious actors want to steal our web browsing activity and that extends into the realm of Ethernet traffic.

Instead of waiting to have your Ethernet data breached, why not be proactive by adding the MACsec protocol in your SoC implementation. Do the math on the cost of building your own MACsec compliant IP, then compare that to what Synopsys has designed and verified already. The semiconductor IP industry has grown steadily for many years now, and for good reason, IP blocks from a trusted vendor can offer a faster path to market while not requiring your engineering team to become domain experts in something new and unfamiliar.

Related Blogs

Podcast EP164: How Weebit Nano is Disrupting the Memory Market with Coby Hanoch

Podcast EP164: How Weebit Nano is Disrupting the Memory Market with Coby Hanoch
by Daniel Nenni on 05-26-2023 at 10:00 am

Dan is joined by Coby Hanoch, Coby joined Weebit Nano as CEO in 2017. He has 15 years of experience in engineering and engineering management roles, and 28 years of experience in sales management and executive roles.

Coby explains the unique features of Weebit Nano’s non-volatile ReRAM technology. He explores the technology’s extended compatibility across advanced process nodes and its speed and power advantages as compared to more traditional approaches such as flash. He discusses current and future deployment for both embedded and discrete applications.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

May 26, 2023May 30, 2023

Micron Mandarin Memory Machinations- CHIPS Act semiconductor equipment hypocrisy

Micron Mandarin Memory Machinations- CHIPS Act semiconductor equipment hypocrisy
by Robert Maire on 05-26-2023 at 6:00 am
Categories: China, Semiconductor Advisors, Semiconductor Services
4 Comments

-We think China issue is overblown- Zero sum game theory
-US should respond Tit-for-Tat and then some- Chop Chinese Chips
-Chip equip makers duplicitous behavior- smacks of hypocrisy
-Exporting chip equip biz/jobs to Asia while asking for CHIPS Act$

Memory Market remains a zero sum game market much like petroleum

China’s “banning” of Micron memory products in China generated a large blowback, in our view overreaction, in Micron’s stock. The reality is that while it may cause some dislocation in the near term, in the longer run there will likely be less impact.

Much like the oil market, memory is a commodity product that is essentially interchangeable with one another. Yes, there may be differences between Texas sweet and Brent, they kind of all burn the same way at the end of the day.

If the US bans the import of Russian or Iranian oil, some other country will buy it instead. Such is the same with memory products. There may be near term dislocation but in the longer run market share between Samsung, SK & Micron will remain similar to today as just the shipping destination will vary.

Its certainly far from the negative impact the stock saw.

The US can speed up the rearrangement of customers

One very easy way to speed up the redistribution of market share would be for the US government to ban any and all Chinese memory products, including memory made by foreign companies in China, from being imported in any product into the US.

In this way Micron will pick up those empty slots while Chinese memory companies will replace Micron in China and we can all go home and call it a day…..

Seems a pretty simple Tit for Tat solution…and effectively nullifies China’s move

We see no reason not to…..

Perhaps up the ante by cutting off 300MM to China?

Right now China is by far the biggest buyer of semiconductor equipment in the world. The US continues to sell China fishing poles even though we have cut off their fish supply….

One problem we have seen is that there is a lot of dancing around which tools can and cannot be sent to China and where in China they can be sent to.

We have heard rumor of some tools being degraded in software in order to be exportable to China or perhaps having the label and name changed to get around export restrictions only to be able to be used for more advanced purposes later. China can even get around a lot of restrictions by multiple patterning and other difficult tricks.

Perhaps the simplest and easiest way is to just restrict China to 200MM (8 inch) and below wafer tools. It essentially would make any and all work arounds impossible, and highly limit how advanced the technology node could be.

It would be super easy to enforce, any idiot with a tape measure could do so. More importantly no dancing around or negotiating specifications and features. Essentially a truly impenetrable technology wall.

Perhaps a Tit for Tat response is not enough….just drop the hammer….

The not so hidden duplicity behind Applied’s “Epic” announcement

We were quite pleased and happy to hear Applied Material’s announced plan to spend billions of dollars on a new “Epic” R&D center in California. Kind of like the existing Maydan center on steroids. The spending and additional hiring over the next few years will be needed in any event to support the expected growth of the semiconductor industry and in order to keep up this is the type of effort that is needed. We view this not as above and beyond spending but spending in line with expectations if we look at current and expected growth and spending rates.

We would note that Applied added an interesting caveat in its press release that this spending is dependent upon CHIPS Act funding. Would they not fund increasing R&D without CHIPS Act money??

Perhaps much more interesting is the juxtaposition of the “Epic” announcement coming six months after another record expansion and spending effort by Applied Materials in Singapore in December. Obviously the celebration of spending all that money and moving many AMAT US jobs to Asia was not accompanied by US government officials in a big splashy announcement.

In December Applied announced “Singapore 2030”. An effort to double its operation in Singapore by building a $600M 700,000 sq foot facility for R&D and manufacturing in Singapore (about three times larger than the 180,000 sq foot “Epic” center in California). It is expected to create well over 1000 direct jobs and many indirect and construction jobs. Singapore is already Applied largest facility outside the US and this expansion will obviously make it larger than a single location in the US.

The spending in Singapore also includes academic partnerships, AI, ML robotics etc;. just like Epic.

If anything , Applied growth in Asia, and specifically Singapore, is at a much higher rate than the US and in fact is likely contributing and causing slowing manufacturing & R&D job growth that would have otherwise happened in Applied in California or Texas.

We find it somewhat amusing that Applied can spend all that money, by itself, in Singapore, creating & moving jobs there while it needs CHIPS Act money to expand in the US?

Is taxpayer CHIPS Act money being used for stock buy backs and dividends?

One other fact we found ironic and interesting juxtaposed timing about the need for CHIPS Act funding for Applied’s Epic center is their earnings announcement just a few days prior……

On the earnings call the CFO Brice said “The board of directors approved a 23% per share dividend increase which is the largest increase in 5 years and supplemented our share buyback program with a new $10 billion repurchase authorization. We believe our free cash flow can continue to grow and support increasing the dividend at an accelerated rate over the next several years which would double our previous dividend per share”

Somehow that does not sound like a company that desperately needs CHIPS Act corporate welfare to afford its baseline R&D spending and new “EPIC” center. Especially after the Singapore expansion.

The optics are even worse in that we are in an “epic” downturn in the industry yet we are accelerating exporting jobs, jacking up shareholder rewards while holding out a hand for CHIPS Act money.

We thought the CHIPS Act was not supposed to support, even indirectly, corporate welfare of shareholder rewards or exporting jobs.

Obviously not……

Lam Leaving Livermore

Applied Materials is far from alone in continuing to move jobs from the US to Asia. It seems part of Lam’s plan of accelerating and increasing manufacturing at its new location in Malaysia is to ramp down and eventually close its manufacturing operation in Livermore California. Essentially moving all those thousands of jobs as well as indirect jobs to Asia in the process.

Lam is also doing quite well despite the downturn and like Applied could make slightly less profit while keeping jobs in the US.

However we haven’t heard about Lam asking for CHIPS Act money……at least not yet.

We have seen this movie before…and it didn’t turn out well…CHIPS Act II

It is amazingly ironic that the semiconductor equipment industry is following in the exact same footsteps of the semiconductor industry that it serves.

Over the last 30 or so years the semiconductor industry exported chip manufacturing to Asia to save costs and increase profits while keeping chip design in the good ole USA.

Now the semiconductor equipment industry is doing the exact same thing despite the huge outcry of what happened to the semiconductor industry itself and now huge rescue and re-shoring efforts that are taking place.

Semi equipment companies are exporting manufacturing while keeping R&D in the US, hence the Epic R&D center, just like the semiconductor industry did and did not work out so well for the industry.

In our view the best way to re-shore the semiconductor industry is to not offshore it in the first place and certainly not support companies that do so for the sake of profitability over patriotism.

The alternative is to have the CHIPS Act II which will be aimed at re-shoring the equipment industry like semi industry before it a few years down the road. It would be much easier to fix right now before we export all equipment manufacturing…..

The very ultimate irony would be for all the new shiny semiconductor fabs being built in the US in Arizona, Idaho, Ohio & Texas etc; to have to import their equipment made in Asia by US companies who moved manufacturing there at the same time the fabs were being built in the US…… how stupid can you get?

Wake up and smell the coffee….

The stocks

While we have no desire to run out and buy Micron shares in the face of the disaster in the memory industry that will be long lived we do believe the sell of was unwarranted and overdone.

If the US does react with restrictions on Chinese memory, which we believe they should, Micron could easily jump back and more.

Nvidia is a shining light in an otherwise dark and gloomy industry and its earnings should help lend some emotional support. We would continue to own (and do so in our personal account) as one of the better and only plays in the semiconductor industry that is seeing a huge success.

With memory in the dumps and foundry/logic not much better we can still wait for better days to own the equipment stocks that are likely overbought in the recent run up.

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

AMAT- Trailing Edge & China Almost Offset Floundering Foundry & Missing Memory

LAM Not Yet at Bottom Memory Worsening Down 50%

ASML Wavering- Supports our Concern of Second Leg Down for Semis- False Bottom

May 25, 2023July 18, 2025

Chiplet Interconnect Challenges and Standards

Chiplet Interconnect Challenges and Standards
by Daniel Payne on 05-25-2023 at 10:00 am
Categories: Chiplet, EDA, Synopsys, TSMC

For decades now I’ve watched the incredible growth of SoCs in terms of die size, transistor count, frequency and complexity. Instead of placing all of the system complexity into a single, monolithic chip, there are now compelling reasons to use a multi-chip approach, like when the maximum die size limit is reached, or it’s more cost effective to use two or more smaller chiplets designed in a variety of technology nodes. Taking the multi-die system path introduces new chiplet interconnect challenges:

Reliable connectivity
High bandwidth
Low power
Low latency
Standards support

Fortunately for the industry there’s been a collective effort to develop standards, and the Universal Chiplet Interconnect Express™ (UCIe™) has gained traction by enabling package-level integration through a die-to-die interconnect along with a connectivity protocol, so that multiple vendors can grow an ecosystem through interoperability. UCIe covers three stack layers, and the PHY layer defines the electrical interface.

Synopsys has been delivering IP for many years now across many domains, like: Interface, Foundation, Processor, Security, Analog, Subsystems. They’ve also joined the UCIe Consortium, contributing to the specification of the standard. There’s a UCIe PHY IP from Synopsys, along with a UCIe Controller IP and verification IP.

Synopsys Multi-die IP

In March 2023 Synopsys announced that their UCIe PHY IP had a tape-out on the TSMC N3E process node.

For reliable connectivity the UCIe standard has up to 8 spare pins per direction, allowing repair of the functional links.

Link Repairs

Variations in the die-to-die interface signals are monitored by Signal Integrity Monitors (SIM), then the Monitoring, Test and Repair controller can determine the health of the multi-die system for predictive maintenance of the links. Synopsys has the Silicon Lifecycle Management tools to monitor the UCIe interface while its operating, detecting soft or hard errors.

Synopsys Monitoring, Test and Repair (MTR) controller

Bandwidth for UCIe using the Synopsys PHY IP is up to 5Tbps/mm efficiency. The Controller IP supports streaming protocols as well as PCI Express and CXL protocols, delivering secure, low-latency data.

Coming up to speed on the UCIe specification takes precious engineering time, so re-using protocol verification IP is going to save your team valuable time to market. Verification IP running on a software simulator provides a good start, then adding hardware emulation with Synopsys ZeBu and prototyping with Synopsys HAPS Platform offer more time savings to debug the whole system running software.

Routing the UCIe signals between dies is automated by the Synopsys 3DIC Compiler tool, and it works for 2.5D chiplets.

Summary

Systems engineers today still have to decide between two approaches for implementation, the traditional single-chip SoC, or the multi-die system. EDA vendors like Synopsys have long been automating the EDA tasks for a single-chip SoC, and they’ve also extended their automation into the realm of 2.5D by developing new EDA tools, verification and IP for multi-die systems.

The interconnect challenges of multi-die systems have been addressed through standardization efforts like UCIe, which lowers the risks for new projects considering chiplet-based systems. Synopsys is one of the few EDA and IP vendors with such broad support of multi-die systems.

Related Blogs

May 24, 2023July 15, 2024

IP Lifecycle Management for Chiplet-Based SoCs

IP Lifecycle Management for Chiplet-Based SoCs
by Kalar Rajendiran on 05-24-2023 at 10:00 am
Categories: EDA, Perforce
2 Comments

Chiplet-based System-on-Chips (SoCs) are becoming increasingly popular in the semiconductor industry due to their potential to improve design efficiency, increase performance, and reduce costs. While chiplets are seen as a way to reduce the cost of innovation, they introduce a lot of challenges too. Packaging, interconnect models, verification, provenance and traceability, IP/design ecosystem management and ensuring security are areas where challenges need to be addressed. Before mass migration to chiplet-based designs can happen, new infrastructure and tools are needed. More complex modeling is needed for interconnects, timing verification, thermal management. Trust concerns around how the chiplets are delivered and integrated into a SoC need to be addressed. This in turn involves making sure chiplets have not been compromised along their way from development through integration to delivery to the foundry/assembly house. Establishing provenance and a traceable integration process becomes a key requirement.

It is in the above context that Simon Butler gave a talk at the IP SoC 2023 conference in Santa Clara last month. He is the General Manager of the Methodics IPLM business unit at Perforce. A chiplet is essentially an IP in the form of a standalone die. Perforce and Simon are no strangers to IP Lifecycle management. Simon walked the audience through laying the foundation for establishing provenance and traceability, bill of materials (BoM) management, and enforcing BoM provenance. Provenance means the origin of something and the history of its ownership, used for establishing authenticity and quality.

Challenges to Establishing Provenance and Traceability

In chiplet-based SoCs, different chiplets can be used in various SoC designs. Therefore, the IP reuse becomes important in order to increase efficiency, reduce cost and time to market. But reusing IP from other designs may cause compatibility issues. In addition, different IP blocks may come from different sources, and knowing the ownership of IP is crucial.

Any system to be used for managing IP should be able to avoid incompatibility issues among all the chiplets and other IP blocks in a chiplet-based SoC. The system should also be able to help avoid IP infringement issues and confirm proper licensing exists. It should also be able to perform authenticity verification to ensure the chiplets were not compromised through backdoors during the manufacturing or delivery process.

Foundation for Establishing Provenance and Traceability

The system should be able to represent IP in a way for identifying the respective design files as well as corresponding metadata model defining the IP’s state and context. While there are many popular version control systems for data/file management, one that includes metadata management is key. Metadata model is where access permissions, quality grade, IP compatibility information, standards compliance details, etc. are maintained. As such, the metadata layer should also offer immutable fields such as timestamps, ownership and other user-defined items.

With the IP representation defined as above, the next critical piece is Bill of Materials (BoM) management.

Bill of Materials (BoM) Management

A BoM is essentially a hierarchically versioned tree of the building block components in a system. As an example, referring to the Figure below, SoC@4 refers to fourth version of the SoC and is guaranteed to contain the respective versions of the sub-components contained in that tree. This ensures traceability and the metadata overlays from the various sub-components provide context. Thus, the BoM can be relied upon as the single source of truth for the configuration management of the SoC. BoM immutability should be enforced at the platform level so that the definition of a version cannot change after a release is made.

Enforcing BoM Provenance

By integrating IP fingerprinting techniques including blockchain-managed signatures for important metadata, immutability of IP contents can be locked down. Queries can be used on such an integrated platform to validate the trustworthiness of the components on the BoM. This helps to mitigate the risk of supply chain attacks, where malicious actors can introduce backdoors or other security vulnerabilities into the product.

Many industries have regulations that require the traceability of components used in electronic products. Enforcing the BoM provenance helps to ensure that the product complies with these regulations and can help with audits and other compliance requirements.

Summary

The best way to ensure BoM provenance is to use a traceable platform such as the one described above. IP release management, built-in traceability, IP discovery and reuse and workspace management across design managers are all included in Methodics IP Lifecycle Management solution.

You can listen toSimon’s talk on-demand here. You can download his presentation slides here.

Also Read:

Overcoming Semiconductor Supply Chain Bottlenecks

The CHIPS and Science Act, Cybersecurity, and Semiconductor Manufacturing

Solve Embedded Development Challenges With IP-Centric Planning

May 24, 2023September 16, 2024

CEO Interview: Issam Nofal of IROC Technologies

CEO Interview: Issam Nofal of IROC Technologies
by Daniel Nenni on 05-24-2023 at 6:00 am
Categories: CEO Interviews, EDA, IROC Technologies

Issam Nofal is the CEO of IROC Technologies and has held various positions with the company for over 23 years as Product Manager, Project Leader, and R&D Engineer. He has authored several papers on test and reliability of Integrated Circuits. He holds a PhD in Microelectronics from Grenoble INP.

What is IROC Technologies’ background?

IROC Technologies is a privately held EDA tools and radiation test service company founded in 2000 by Dr. Michael Nicolaidis, a researcher at the CNRS-France. He has worked closely with the TIMA laboratory. Dr. Nicolaidis is well known from his contributions in the test and reliability domains of Integrated Circuits.

The main idea behind the creation of IROC was to develop solutions for functional reliability threats caused by soft errors in modern semiconductor systems. The radiation effects on microelectronic systems were well known in the harsh environment of space, but with the increased use of deep submicron technologies these effects have become a serious threat to the reliability of ground level applications. Solutions to deal with this new challenge are now mandatory to achieve high reliability in semiconductor designs.

Main system integrators like CISCO and big foundries, such as TSMC, became aware of the soft error phenomena and the need for solutions to predict and evaluate Soft Error Rates of components and systems. This, in turn, helped to “evangelize” chip manufacturers and designers to take the soft error threat into account either by mitigating the design’s propensity to soft errors, or by selecting more resilient technology processes. In the last 22 years, IROC has worked closely with foundries, top semiconductor companies, and government programs to offer solutions and services that help them achieve this objective.

What products/services does IROC offer?

IROC helps the entire semiconductor value chain to reduce soft errors in designs by offering EDA tool solutions to predict the SER early in the design cycle. We also offer expert design consulting from component through system characterization and testing.

IROC products are based on a deep understanding of the soft error phenomena starting from the ionizing particles effects at transistor level and ending by the analysis of its effects on the functionality of the final system. They cover both cell level soft error simulation using TFIT, and the analysis and quantification of error propagation at circuit or SoC level using SoCFIT.

In addition to the EDA solutions, we provide radiation test services for High Energy Neutron, Thermal Neutron, Heavy Ions, Protons, Co-60, and Alpha, at the best test facilities in the world such as LANL, TRIUMF, and ISIS. We also deliver support and design consulting for management and mitigation of Soft Error Rate in complex components and systems.

What makes IROC’s EDA tools and services unique?

We collaborate with major foundries such as TSMC, Samsung, and Global Foundries to build accurate models for TFIT. Thanks to this collaboration, TFIT models for mainstream process nodes are built in conjunction with the foundry using process information not readily available with standard PDKs. The TFIT model for a given process characterizes the process sensitivity to ionizing particles, which can be used by TFIT to simulate any cell or custom design implemented in the target process. This unique foundry model enables TFIT to simulate the Soft Error Rate up to one hundred times (100X) faster than the best TCAD based solutions.

SoCFIT analyzes the propagation of errors from cell to system level. SoCFIT supports big designs with millions of Flip-Flops and memory blocks. The Soft Error Rate (SER) of the SoC can be calculated at high speed and mitigation solutions proposed to reduce SER with minimal area overhead.

IROC’s Test Services team has more than 20 years of experience with shuttle test campaigns, component/system test, and alpha test/count. We customize our services to our customer’s needs, from complete solutions to partial requirements. We leverage our close relationships with international testing facilities to provide the best service to our customers.

IROC also provides consulting services to customers with complex systems vulnerability analysis requirements. We use our expertise and TFIT/SoCFIT tools to provide total system error rate and identify critical parts of the design requiring reliability improvements at the cell, or SoC level.

Who is interested in your offerings?

Our customers are in the automotive, aerospace, healthcare, and HPC segments. Any semiconductor company with high reliability standards requirements can benefit from our unique foundry models, TFIT, SoCFIT, our specialized consulting, and testing services.

What are IROC’s upcoming plans?

We are continuously adding capabilities to our EDA solutions, while providing consistent high quality service offerings. We are adding new features to TFIT and SoCFIT to fit new market requirements. We will also continue to collaborate closely with foundries to add models for their latest technology process nodes.

We are working on the certification of SoCFIT according to the ISO 26262 standard and continue to investigate other safety standards that can benefit our customers concerned by functional safety.

We will soon announce our new website reflecting how our customers are using and benefiting from our unique radiation expertise and our EDA software solutions.

Visit our new website at https://www.iroctech.com/

How do customers engage with IROC?

Customers are turning to us for Soft Error analysis and mitigation using TFIT or SoCFIT and Radiation testing services. Email info@iroctech.com or visit https://www.iroctech.com/ to see how we can help you.

Also Read:

CEO Interview: Ravi Thummarukudy of Mobiveil

Developing the Lowest Power IoT Devices with Russell Mohn

CTO Interview: Dr. Zakir Hussain Syed of Infinisim

May 23, 2023July 18, 2025

Driving the Future of HPC Through 224G Ethernet IP

Driving the Future of HPC Through 224G Ethernet IP
by Kalar Rajendiran on 05-23-2023 at 10:00 am
Categories: EDA, IP, Synopsys

The need for speed is a never-ending story when it comes to data communications. Currently there are a number of trends such as cloud computing, artificial intelligence, Internet of Things (IoT), multimedia applications and consumer expectations driving this demand. All of these trends are accelerating the growth in high-performance-computing (HPC) and the traditional data center server architecture is evolving into a hyper-converged server box architecture. A hyperconverged server box is a type of server infrastructure that combines storage, compute, and networking resources into a single, integrated appliance. It is designed to simplify data center management and reduce infrastructure costs by consolidating multiple functions into a single device. As the industry moves to 224G connectivity rate, there are a number of design considerations and decisions to make to overcome the numerous implementation challenges.

Synopsys’ first demonstration of 224G SerDes was in Basel, Switzerland at the 2022 European Conference on Optical Communication (ECOC). As the first company to demonstrate 224G SerDes, Synopsys has valuable insights to offer. At the recently held IPSoC 2023 conference, Manmeet Walia made a detailed presentation on this subject matter. Manmeet is Director of Product Management at Synopsys for high-speed interface IPs which include PCI-e, Die-to-Die (D2D) and Ethernet.

Why is 224G Ethernet SerDes Needed?

224G Ethernet is needed for a number of reasons. To start with, it is needed for addressing the increasing demand discussed earlier, for higher data rates in modern data centers. The networks within data centers are flattening to reduce latencies, which drives the demand for higher bandwidth connections. Switch SoC die sizes are hitting the maximum reticle size limit, which means the higher connectivity rates are needed to support the higher bandwidth requirement. Server rack unit density, power dissipation and thermal management requirements are also driving the need for 224G connectivity. Additionally, 224G Ethernet helps reduce the number of cables and switches required in high-density data center environments, which can improve network efficiency and reduce costs. In addition, it provides backward compatibility with existing Ethernet standards, allowing for easy integration into existing networks.

Challenges to Delivering 224G

There are several areas of challenges when it comes to implementing and deploying 224G Ethernet. The laws of semiconductor physics are not keeping pace with Serial Link throughout demands. Link loss is going up as package/connector/channel technologies are not keeping pace with the demand. As physical distance on the Front Pluggable Panel has not reduced, reflections get worse. As isolation has not improved, crosstalk gets worse. The overall complexity for implementation increases 5x when increasing speed from 112G to 224G.

Challenges Being Addressed

There are a number of aspects to be considered and optimal choices arrived at, starting with the signaling scheme. While the PAM6 scheme delivers less Nyquist loss, PAM4 prevails for most use cases due to better signal-to-noise (SNR) ratio and lower FEC overhead. At the 224G SerDes architecture level, analog circuitry must be minimized for reduced parasitics and high bandwidth front end. And rigorous sensitivity analysis must be performed on individual analog blocks to reduce any impairments. Innovative digital signal processing (DSP) techniques are critical to compensate for the gain errors, skew mismatches and to achieve better noise immunity.

And parallelism should be the theme for high-speed processing efficiency when it comes to the high-level architecture for a 224G SerDes. Optics technology is also moving closer to the host SoC to address power and performance issues as we move to 224G.

Summary

224G Ethernet is fast driving the growth of HPC applications, with the licensing of 224G IP projected to crossover 112G IP by 2025. Early adopter applications include Retimers, Switches, AI Scaling, optical modules, I/O chiplets and FPGAs. Synopsys provides a complete solution with lowest power, area and latency to make it easy for customers to integrate, validate and go to production.

For more details on Synopsys 224G IP, visit here.

To listen to Manmeet’s talk at IPSoC 2023, visit here.

Also Read:

Curvilinear Mask Patterning for Maximizing Lithography Capability

Chiplet Q&A with Henry Sheng of Synopsys

Synopsys Accelerates First-Pass Silicon Success for Banias Labs’ Networking SoC