How to meet 3Ps in 3D-ICs with sub-20nm Dies?

How to meet 3Ps in 3D-ICs with sub-20nm Dies?
by Pawan Fangaria on 03-06-2014 at 1:30 am

It feels to be at the top of semiconductor technology by having dies with high density of semiconductor design at sub-20nm technology node stacked together into a 3D-IC to form a complete SoC which can accommodate billions of gates. However there are multiple factors to be looked at in order to make that successful amid often conflicting… Read More


Mixed-Signal SoC Debugging & IP Integration Made Easy

Mixed-Signal SoC Debugging & IP Integration Made Easy
by Pawan Fangaria on 02-28-2014 at 7:30 am

A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly.… Read More


SoC Functional Verification Planning and Management Goes Big

SoC Functional Verification Planning and Management Goes Big
by Daniel Payne on 02-24-2014 at 10:01 am

Big SoC designs typically break existing EDA tools and old methodologies, which then give rise to new EDA tools and methodologies out of necessity. Such is the case with the daunting task of verification planning and management where terabytes of data have simply swamped older EDA tools, making them unpleasant and ineffective… Read More


Xilinx: Delivering a Generation Ahead

Xilinx: Delivering a Generation Ahead
by Paul McLellan on 02-19-2014 at 4:15 pm

Last week was Xilinx’s investor day. Xilinx believe they are now a process generation ahead. They did over $100M in 28nm designs in FY2013 (Xilinx FY ended March 2013) and did over over $100M in Q4 2013 calendar year alone (and this is almost all true production volume, with only about 5% prototypes) with a plan greater than … Read More


Carbon Design Systems – Secret of Success

Carbon Design Systems – Secret of Success
by Pawan Fangaria on 02-19-2014 at 11:00 am


Last week, after learning from the press releaseof Carbonabout its rocking sustained growth with record-breaking revenue and a thumping 46% increase in bookings, I was interested to know some more details about what drives Carbon to such an amazing performance in an EDA market that is generally prone to growth of a few percentage… Read More


Power Control Moving into Hardware

Power Control Moving into Hardware
by Paul McLellan on 02-14-2014 at 6:30 pm

Sonics have been building networks-on-chips (NoCs) for a long time and have amassed a rich patent portfolio. So being granted a new one isn’t usually deemed press-release-worthy. However, their latest patent on power management is pretty significant. It is patent 8,601,288 titled “Intelligent Power Controller”.

Historically… Read More


Happy Birthday Xilinx

Happy Birthday Xilinx
by Luke Miller on 02-14-2014 at 4:00 pm

I have never done this before, wished a company happy birthday. So here goes, Happy Birthday Xilinx! How does it feel to be 30? Looking good eh? Signing up for AARP? My family and I just sang and had cake and ice cream. They did look at me like I was nuts when I set a place at the table for a Xilinx FPGA. In all seriousness, over the years Xilinx… Read More


Will Google Design Server SoCs?

Will Google Design Server SoCs?
by Beth Martin on 02-13-2014 at 12:22 pm

Google is search, of course, but it is also OS (Android), systems (Glass) and increasingly, maybe, hardware. Rumors are swirling that through careful acquisitions and focused internal development, Google is set to make its own server SoCs.

Google’s Larry Page has stated that they are in the hardware business. They’ve been making… Read More


SoC Verification Closure Pushes New Paradigms

SoC Verification Closure Pushes New Paradigms
by Pawan Fangaria on 02-06-2014 at 10:00 am

In the current decade of SoCs, semiconductor design size and complexity has grown by unprecedented scale in terms of gate density, number of IPs, memory blocks, analog and digital content and so on; and yet expected to increase further by many folds. Given that level of design, it’s imperative that SoC verification challenge has… Read More


Intel Quark awakening from stasis on a yet-to-be-named planet

Intel Quark awakening from stasis on a yet-to-be-named planet
by Don Dingee on 02-05-2014 at 3:00 pm

We know the science fiction plot device from its numerous uses: in order to survive a journey of bazillions of miles across galaxies into the unknown future, astronauts are placed into cryogenic stasis. Literally frozen in time, the idea is they exit a lengthy suspension without aging, ready to go to work immediately on revival … Read More